Siheng Zhu

A 5-GHz low-phase-noise CMOS LC-VCO for China ETC applications

A 5-GHz fully integrated for China ETC applications, low-phase-noise and wide-band LC voltage controlled oscillator is presented. Low-phase-noise has been achieved by using control line filtering technology and avoiding the tail current source. The circuit is implemented in the 0.18um TSMC CMOS process. The oscillator is tuned from 5.27 to 6.41 GHz with switched capacitors. This VCO consumes 5.6mA from a 1.8V supply and features a phase noise of −117 dBc/Hz at 1 MHz frequency offset.

Design and optimization of dual modulus prescaler using the extended true-single-phase-clock

A low-power divide-by-4/5 unit of a prescaler is proposed. The power consumption and operating frequency of the extended true-single-phase-clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are analyzed. Compared with the existing design, a 20% reduction of power consumption is achieved. A divide-by-16/17 dual-modulus prescaler implemented with this divide-by-4/5 unit using a 0.18-um CMOS process is capable of operating up to 4.1 GHz with a low-power comsumpti-on. The prescaler is implemented in low-power high-resolution frequency dividers for wireless short distance application.

New two-dimensional PBG structures for THz transmission line and antenna integrated design based on MEMS technology

Based on MEMS technology and finite element analysis (FEA), we design multi-kinds of efficient integrated functional elements utilizing two-dimensional (2-D) photonic bandgap (PBG) structures at 0.5 Terahertz (THz). The functional elements are integrated in the same silicon substrate using the micromachining technology for Micro-Electro-Mechanical Systems (MEMS), which can be used to construct easily the THz integrated systems. Consequently, the integrated design of the antenna-feed system is realized. The benefits of the integrated design lie in high efficient transmission and radiation, high reliability and high consistency. And the further improvement of the performance guidelines has a good perspective.

A low voltage CMOS rail-to-rail operational amplifier based on flipped differential pairs

This paper introduces a CMOS operational amplifier with constant transconductance, suitable for operation in low voltage environments. A constant transconductance is ensured for the whole common mode input stage which is based on flipped differential pairs. The proposed operational amplifier is designed to operate with a 1-V supply and is implemented in 0.18-μm standard CMOS technology. The results show that a closed-loop unity-gain bandwidth achieves 7.6 MHz and an open-loop low-frequency gain is higher than 73 dB with a 1-MΩ‖15-pF load.

A 5.8 GHz CMOS low noise amplifier for electronic toll collection system

This paper presents a 5.8 GHz low noise amplifier (LNA) for electronic toll collection system (ETCS). Traditional design strategy of source inductor feedback amplifier (L-CSLNA) ignores the influence of off chip matching, such as print circuit broad (PCB), bonding wire and passive chip parts which greatly affect the performance of LNA at high frequency. In this paper we adopt 3D electromagnetic simulation to analyze the impacts of off chip components to the design of LNA. The proposed LNA has been fabricated in 0.18 μm CMOS process. The measured S11 of the proposed LNA is less than -10 dBm from 5.7 to 5.9 GHz, the minimal noise figure (NF) is 2 dB, the maximal power gain is 12.7 dB and the IIP3 is -4 dBm with 16 mW power dissipation.

Design of low power wake-up circuits applied to OBU system chip

With supplied by the battery, the low power consumption of OBU system chip in ETCS is demanded. This paper designs a low power wake-up circuits applied to OBU system chip. The circuit system extracts envelope signal from an amplitude shift keying (ASK) modulated 5.8 GHz carrier and converts it to digital signal. Only the envelop signal that the frequency of it is 14 KHz can produce the wake-up pulse, which effectively prevents error wake-up caused by other frequency signals. By incorporating an input impedance matching network, the wake-up circuits achieve input sensitivity of -35 dBm and the S11 of the match network is -19 dB with 50 Ω input impedance. Measurement results show the dc current is 6 μA from 2.4 V to 5 V supply. The wake-up circuits is fabricated in TSMC 0.18 μm RF CMOS 1P6M process and the entire chip occupies an areas of 375×330 μm2.

A 5.8 GHz CMOS ASK demodulator for the China electronic toll collection system

In this paper, a 5.8 GHz integrated CMOS amplitude shift keying (ASK) demodulator for the China electronic toll collection system (ETCS) is presented. The ASK demodulator modulates the 256 Kbps baseband signal with reference to the 5.8 GHz carrier frequency for low power dissipation. The design is implemented in a 0.18 μm CMOS process. The measurement results show that the proposed ASK demodulator can receive power as low as −38dBm with a 5.8 GHz carrier frequency, and modulation index can range from 30% to 100%. The circuit dissipates 200 μA with 1.8 V supply voltage and has a core die area of 0.17 mm2.

A low-power decibel-linear CMOS Automatic Gain Control

This paper presents an all CMOS decibel-linear Automatic Gain Control (AGC). This AGC achieves large dynamic range with low power consumption. By applying digital switches to change exponential approximation function, four dynamic ranges (62, 50, 33, 26 dB) are realized. This AGC is implemented in TSMC 0.18-μm CMOS RF process. Measurement results show that this AGC achieves 60 dB linear range with linearity error less than 1 dB. The whole circuit consumes 3.6 mA from 2-V supply.

A low-power-consumption linear-in-dB CMOS VGA

This paper presents a low-power and small-size variable gain amplifier (VGA) which consumes only 1.1mW and occupies only 132um × 59um in 0.18-um CMOS technology. The proposed circuit is implemented by Gilbert cells and an exponential function circuit for the dB linearity of the gain voltage. The gain of the VGA can be varied linearly in dB from -10dB to 50dB with respect to a control voltage from 0.2V to 0.85V. The operation frequency is only 10MHz, but the VGA maintains 3dB-bandwidth wider than 46MHz throughout its gain range. At the worst case, the amplitude of the output can be 300mV when THD is lower than -40dBc. The total simulation is based on TSMC 0.18um. Low power consumption is obtained owing to high transition frequency of the transistors in 0.18-um CMOS technology.

A 20MHz continuous-time Gm-C filter with source degeneration linearization technique

A fifth-order Gm-C low-pass filter, which employs source degeneration linearization technique, used in analog frontend anti-aliasing is presented. This filter was simulated in the TSMC 0.18-μm CMOS process design kit (PDK) with 5-fF/μm2 MIM capacitors. This simulated filter features corner frequency of 20MHz, power consumption less than 4mW, supply voltage of 2V, THD of 1% at 260mVpp. The total area of this design is less than 0.2mm2.