Simon Hauger

Evaluation of Router Implementations for Explicit Congestion Control Schemes

Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require additional packet processing in every router and therefore raise the question whether, and how, this can be achieved in high-speed routers. This paper investigates the realization complexity of these router functions of two such schemes, the TCP Quick-Start extension and the Explicit Control Protocol (XCP). Our focus lies on the implementation using a network processor. We show that synchronization issues among parallel processing entities have to be considered, and that this affects the router performance. We develop and compare different synchronization mechanisms for highly parallel packet processing. Our prototype implementation on an Intel IXP network processor allows to quantify the impact on throughput and delay caused by the additional packet processing in the fast path. The measurements reveal that Quick-Start and XCP processing is feasible at multiple Gbit/s line speed, with Quick-Start being simpler to scale. We expect similar results for the implementation of the Rate Control Protocol (RCP), which is another router-assisted congestion control scheme, requiring no elaborate synchronization. Finally, we study the implementation using programmable logic and show the applicability of XCP and in particular Quick-Start even at significantly higher line speeds.

Performance comparison of router assisted congestion control protocols: XCP vs. RCP

In the current Internet, network overload is prevented by the congestion control of the Transmission Control Protocol (TCP). The traditional TCP congestion control is an end-to-end mechanism that suffers from some inherent shortcomings. A design alternative for the Future Internet is to use more feedback from the routers. Such router-assisted congestion control schemes can achieve a more efficient utilization of network resources and better fairness, even in environments with large bandwidth-delay products. Two promising proposals are the eXplicit Control Protocol (XCP) and the Rate Control Protocol (RCP). This paper evaluates the performance of XCP and RCP and compares them with the existing TCP congestion control. In order to verify previous work, a new simulation tool has been developed independently of the existing ns-2 code basis. This simulator is used to study the basic behavior of the algorithms and to analyze several degrees of freedom in the protocol design. Furthermore, the performance of the different approaches is compared using realistic Internet traffic scenarios. The results show that indeed both XCP and RCP efficiently utilize the link capacity without requiring packet loss. Unlike XCP, RCP improves the reactivity of data transfers by reducing the flow completion time. These results confirm previously published results and show that in particular RCP has the potential to replace TCP congestion control in the Future Internet.

A novel architecture for a high-performance network processing unit: Flexibility at multiple levels of abstraction

Network processing devices in future, high-speed network nodes have to be capable of processing several hundred million packets per second. Additionally, they have to be easily adaptable to new processing tasks due to the introduction of new services or protocols. Field programmable gate arrays (FPGAs) and network processors are suitable devices fulfilling these requirements: The former offer configurability at registertransfer level providing fine grain adaptability to unforeseen processing requirements and a high processing power. The latter are programmed at the more abstract software level and support high-speed execution of their fixed set of instructions. In this paper, we present a novel architecture for an FPGA-based highspeed network processing unit offering programmable modules at multiple levels of abstraction: register-transfer level, microcode level, software level and parameter level. A prototypical implementation demonstrates its feasibility with todays field programmable gate array devices offering a throughput of more than one hundred million minimum sized packets per second.

Quick-Start and XCP on a network processor: Implementation issues and performance evaluation

The quick-start extension of the transmission control protocol (TCP), as well as the explicit control protocol (XCP), are experimental congestion control schemes that use router feedback to overcome limitations of TCPpsilas standard mechanisms. Both approaches require additional packet processing in every router and therefore raise the question whether, and how, this can be achieved in high-speed routers. This paper studies the realization complexity of the quick-start and XCP router functions on a network processor. We show that in both cases synchronization issues among parallel processing entities have to be considered, and that this affects the router performance. We develop and compare different synchronization mechanisms for highly parallel packet processing. Our prototype implementation on an Intel IXP network processor allows to quantify the impact on throughput and delay caused by the additional packet processing in the fast path. The measurements reveal that quick-start and XCP processing is feasible at multiple Gbit/s line speed, with quick-start being simpler to scale.

Design and Evaluation of a Burst Assembly Unit for Optical Burst Switching on a Network Processor

Optical Burst Switching (OBS) has been proposed in the late 1990s as a novel photonic network architecture directed towards efficient transport of IP traffic. OBS aims at cost-efficient and dynamic provisioning of sub-wavelength granularity by optimally combining electronics and optics. In order to reduce the number of switching decisions in OBS core nodes, traffic is aggregated and assembled to bursts by the Burst Assembly Unit in an OBS ingress edge node. This Burst Assembly Unit is responsible for buffering incoming packets in queues and sending them as bursts as soon as a minimum burst length is reached and/or a timer expires. Typically, dozens of different queues must be able to handle high volumes of traffic.

Designing high-speed packet processing tasks at arbitrary levels of abstraction: implementation and evaluation of a MIXMAP system

Packet processing systems of forthcoming high-speed network nodes demand extremely high processing rates, but also modularity and easy adaptability due to new or evolving protocols and services. As the fixed architecture and instruction set of current network processors sometimes hinders an efficient implementation of processing tasks, we introduced the MIXMAP architecture [4] that is designed to offer programmability at multiple levels of abstraction. Now we describe the prototypical realization of this architecture showing its feasibility. Our results indicate that up to 170 million packets per second can be processed with this architecture using current FPGAs. By implementing packet processing tasks at register-transfer level and at software level, we validate the architectures applicability and the benefits of implementing at an appropriate level of abstraction.