Simon Künzli

Indicator-Based Selection in Multiobjective Search

This paper discusses how preference information of the decision maker can in general be integrated into multiobjective search. The main idea is to first define the optimization goal in terms of a binary performance measure (indicator) and then to directly use this measure in the selection process. To this end, we propose a general indicator-based evolutionary algorithm (IBEA) that can be combined with arbitrary indicators. In contrast to existing algorithms, IBEA can be adapted to the preferences of the user and moreover does not require any additional diversity preservation mechanism such as fitness sharing to be used. It is shown on several continuous and discrete benchmark problems that IBEA can substantially improve on the results generated by two popular algorithms, namely NSGA-II and SPEA2, with respect to different performance measures.

A General Framework for Analysing System Properties in Platform-Based Embedded System Designs

We present a framework (real-time calculus) for analysing various system properties pertaining to timing analysis, loads on various components and on-chip buffer memory requirements of heterogeneous platform-based architectures, in a single coherent way. Many previous analysis techniques from the real-time systems domain, which are based on standard event models, turn out to be special cases of our framework. We illustrate this using various realistic examples.

Chapter 4 – Design Space Exploration of Network Processor Architectures

It is noted that network processors (NPs) generally consist of multiple processing units such as CPU cores, microengines, and dedicated hardware for computing-intensive tasks, memory units, caches, interconnections, and I/O interfaces. Following a system-on-a-chip (SoC) design method, these resources are then put on a single chip and they must interoperate in order to perform packet processing tasks at line speed. The process of determining the optimal hardware and software architecture for such processors includes issues involving resource allocation and partitioning. The chapter presents a framework for the design space exploration of embedded systems. It is observed that the architecture exploration and evaluation of network processors involve many tradeoffs and a complex interplay between hardware and software. The chapter focuses on high level of abstraction, where the goal is to quickly identify interesting architectures that can be further evaluated by taking lower-level details into account. Task models, task scheduling, operating system issues, and packet processor architectures collectively play a role in different phases of the design space exploration of packet processor devices.

Workload characterization model for tasks with variable execution demand

The analysis of real-time properties of an embedded system usually relies on the worst-case execution times (WCET) of the tasks to be executed. In contrast to that, in real world applications the running time of tasks may vary from execution to execution, e.g. in multimedia applications. The traditional worst-case analysis of the system then returns overly pessimistic estimates of the system performance. In this paper we propose a new effective method to characterize tasks with variable execution requirements, which leads to tighter worst-case bounds on system performance and better use of available resources. We show the applicability of our approach by a detailed study of a multimedia application.

Rate analysis for streaming applications with on-chip buffer constraints

While mapping a streaming (such as multimedia or network packet processing) application onto a specified architecture, an important issue is to determine the input stream rates that can be supported by the architecture for any given mapping. This is subject to typical constraints such as on-chip buffers should not overflow, and specified playout buffers (which feed audio or video devices) should not underflow, so that the quality of the audio/video output is maintained. The main difficulty in this problem arises from the high variability in execution times of stream processing algorithms, coupled with the bursty nature of the streams to be processed. In this paper we present a mathematical framework for such a rate analysis for streaming applications, and illustrate its feasibility through a detailed case study of a MPEG-2 decoder application. When integrated into a tool for automated design-space exploration, such an analysis can be used for fast performance evaluation of different stream processing architectures.

Combined approach to system level performance analysis of embedded systems

Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume certain system architectures and application domains, and are thus tailored to give tight analysis results for specific systems. We consider two different compositional analysis methods. Both methods have their particular strengths for different architectures and applications. In this paper, we aim to enhance the analysis capabilities for these techniques. A method for event model conversion allows us a seamless integration of the two methods. Finally, we present a detailed case study to show the applicability and benefits of the enhanced performance analysis technique.

DiMo: distributed node monitoring in wireless sensor networks

Safety-critical wireless sensor networks, such as a distributed fire- or burglar-alarm system, require that all sensor nodes are up and functional. If an event is triggered on a node, this information must be forwarded immediately to the sink, without setting up a route on demand or having to find an alternate route in case of a node or link failure. Therefore, failures of nodes must be known at all times and in case of a detected failure, an immediate notification must be sent to the network operator. There is usually a bounded time limit, e.g., five minutes, for the system to report network or node failure. This paper presents DiMo, a distributed and scalable solution for monitoring the nodes and the topology, along with a redundant topology for increased robustness. Compared to existing solutions, which traditionally assume a continuous data-flow from all nodes in the network, DiMo observes the nodes and the topology locally. DiMo only reports to the sink if a node is potentially failed, which greatly reduces the message overhead and energy consumption. DiMo timely reports failed nodes and % greatly minimizes the false-positive rate and energy consumption compared with other prominent solutions for node monitoring.

Evaluating schedulers for multimedia processing on buffer-constrained SoC platforms

Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.

Distinguishing attacks on t-functions

Klimov and Shamir proposed a new class of simple cryptographic primitives named T-functions. For two concrete proposals based on the squaring operation, a single word T-function and a previously unbroken multi-word T-function with a 256-bit state, we describe an efficient distinguishing attack having a 232 data complexity. Furthermore, Hong et al. recently proposed two fully specified stream ciphers, consisting of multi-word T-functions with 128-bit states and filtering functions. We describe distinguishing attacks having a 222 and a 234 data complexity, respectively. The attacks have been implemented.

Schedulability of event-driven code blocks in real-time embedded systems

Many real-time embedded systems involve a collection of independently executing event-driven code blocks, having hard real-time constraints. Tasks in many such systems, like network processors, are either not preemptable or have restrictions on the number of preemptions allowed. All the previous work on the schedulability analysis of such systems either have exponential complexity, or allow unbounded number of preemptions and are usually based on heuristics. In this paper we present the exact necessary and sufficient conditions under EDF, for the schedulability of such a collection of code blocks in a non-preemptive environment, and give efficient algorithms for testing them. We validate our analytical results with experiments and show that the schedulability analysis problem in such systems can be exactly and efficiently solved in practice.