Simon Wunderlich

Network Coding in Heterogeneous Multicore IoT Nodes With DAG Scheduling of Parallel Matrix Block Operations

Random linear network coding (RLNC) has the potential to improve the performance of current and future Internet of Things (IoT) communication systems, but is computationally demanding due to matrix multiplications and inversions. Some single-core RLNC implementations achieve already sufficient coding speeds for contemporary multimedia streaming formats. However, advances in multimedia streaming formats and IoT applications will require the exploitation of heterogeneous multicore architectures, which are becoming common for a wide range of IoT nodes, including smartphones. In this paper, we introduce and evaluate efficient RLNC computing strategies for IoT node architectures, including the emerging heterogeneous big.LITTLE multicore architectures with multiple big (fast) cores and multiple LITTLE (slow) cores. In contrast to existing RLNC implementation strategies, we build on and adapt highly optimized dense matrix operations from the high performance computing field to RLNC on heterogeneous multicore IoT nodes. Our approach includes the optimization of RLNC matrix operations through optimized operations on matrix blocks with single instruction multiple data instructions. We schedule block operations on the heterogeneous cores through a directed acyclic graph that avoids artificial synchronization points while ensuring the data dependencies. We examine priority scheduling according to the number of outgoing dependencies of a task and data locality of cached blocks. Our extensive measurements with several heterogeneous big.LITTLE multicore IoT node and smartphone processor boards demonstrate higher RLNC encoding and decoding throughputs than existing approaches. Moreover, our measurements indicate that the utilization of more cores decreases energy consumption, which is an important goal for IoT nodes.

Caterpillar RLNC (CRLNC): A Practical Finite Sliding Window RLNC Approach

Random linear network coding (RLNC) is a popular coding scheme for improving communication and content distribution over lossy channels. For packet streaming applications, such as video streaming and general IP packet streams, recent research has shown that sliding window RLNC approaches can reduce the in-order delay compared with block-based RLNC. However, existing sliding window RLNC approaches have prohibitive computational complexity or require feedback from the receivers to the sender. We introduce caterpillar RLNC (CRLNC), a practical finite sliding window RLNC approach that does not require feedback. CRLNC requires only simple modifications of the encoded packet structure and elementary pre-processing steps of the received coded packets before feeding the received coding coefficients and symbols into a standard block-based RLNC decoder. We demonstrate through extensive simulations that CRLNC achieves the reliability and low computational complexity of block-based RLNC, while achieving the low in-order delays of sliding window RLNC.

We don't need no generation - a practical approach to sliding window RLNC

Random Linear Network Coding (RLNC) is a popular coding scheme to improve communication over lossy channels. For packet streaming applications (video streaming, general IP streams), recent research has shown that sliding window schemes can improve in-order delay properties compared to the block/-generation based coding. However, implementing sliding window RLNC with a limited coding window poses new challenges in both theoretical and engineering aspects. We introduce the first practical generation-less sliding window RLNC scheme, which is built on existing generation based coders. Through discrete simulation and a proof of concept implementation, we show that, the in-order delay can be improved compared to generation based schemes while retaining the reliability, computational complexity and overhead.

PACE: Redundancy Engineering in RLNC for Low-Latency Communication

Random linear network coding (RLNC) is attractive for data transfer as well as data storage and retrieval in complex and unreliable settings. The existing systematic RLNC approach first sends all source symbols in a generation without encoding followed by the coded redundant packets at the tail of the generation. This systematic tail RLNC achieves low delay when packet drops are rare; however, recovery of any dropped source symbol requires to wait for the coded packets at the end of the generation. We propose and evaluate a novel PACE RLNC approach that paces the transmissions of coded redundant packets throughout the generation of source symbols. The paced coded packets enable the recovery of dropped source symbols without waiting for the tail end of the generation. More specifically, we propose PACE-Uniform, which uniformly intersperses individual coded packets throughout the generation, and PACE-Burst, which intersperses bursts of code packets. Our extensive simulation evaluations indicate that PACE-Uniform significantly reduces the mean source symbol delay compared to tail RLNC, while achieving nearly the same loss probability. We also demonstrate that PACE-Burst generalizes the concept of pacing the redundant packet transmissions and can be flexibly tuned between PACE-Uniform and the conventional tail RLNC by controlling the number of coded packets in a burst.

Network Coding Parallelization Based on Matrix Operations for Multicore Architectures

Network coding has the potential to improve the performance of current and future communication systems (including transportation and storage) and is currently even considered for communication architectures between the individual processors on same board or different boards in close proximity. Despite the fact that single core implementations show already comparable coding speeds with standard coding approaches, this paper pushes network coding to the next level by exploiting multicore architectures. The disruptive idea presented in the paper is to break with current software implementations and coding approaches and to adopt highly optimized dense matrix operations from the high performance computation field for network coding in order to increase the coding speed. The paper presents the novel coding approach for multicore architectures and shows coding speed gains on a commercial platform such as the Raspberry Pi2 with four cores in the order of up to one full magnitude. The speed increase gain is even higher than the number of cores of the Raspberry Pi2 since the newly introduced approach exploits the cache architecture way better than by-the-book matrix operations.