Sing W. Chin

A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller

This paper describes the design and implementation of a fully monolithic 16-b, 1 Msample/s, low-power A/D converter (ADC). An on-chip 32-b custom microcontroller calibrates and corrects the pipeline linearity to within 0.75 LSB integral nonlinearity (INL) and 0.6 LSB differential nonlinearity (DNL). High speed and low power are achieved using a pipelined architecture. Errors resulting from capacitor mismatches, finite op-amp open loop gain, charge injection and comparator offset are removed through self-calibration. Coefficients determined during calibration are stored on chip, digitally correcting the pipeline ADC in real time during normal conversion, Full-scale errors are removed through self-calibration and an-chip multiplication. Linearity errors due to capacitor voltage coefficients are reduced using a curve fit algorithm and on-chip ROM. Digital cross-talk errors resulting from the microcontroller running at a rate of ten times the analog sampling rate have prevented implementations of fully monolithic converters of this performance class in the past. Mismatches in cross-talk due to different digital timing between calibration and correction lead to linearity errors at critical correction points. Experimental analysis and circuit techniques which overcome these problems are presented.

A multistep A/D converter family with efficient architecture

A family of 8- and 10-b analog/digital converters (ADCs) has been designed using a more efficient architecture. The 10-b ADC requires two 4-b (two 3-b for the 8-b converter) half-flash cycles and a self-corrected voltage estimator. While the speed is similar to that of conventional half-flash ADCs, power consumption and die size are lower due to reduced numbers of comparators and resistors. The flash steps can be reduced by 1 b each, for an overall reduction in comparator count by a factor of 2. This architecture can be used to reduce the comparator and resistor count of any existing half-flash ADCs, ultimately decreasing die area and power consumption. For the same process and resolution, this architecture reduces die size and power consumption by 50%. >

A low-power 1 MHz, 25 mW 12-bit time-interleaved analog-to-digital converter

A 12-bit 1 Msample/s 25 mW analog-to-digital converter was designed. Linearity, offset, and gain errors of less than 1/2 LSB have been achieved using an EEPROM memory trimming scheme. The EEPROM memory array, programmed during testing, continuously drives a correction digital-to-analog converter (DAC) with code dependent correction factors. The analog-to-digital converter (ADC) uses a time-interleaved multistep architecture consisting of two banks of comparator arrays sharing a common reference ladder and EEPROM correction memory. A static EEPROM memory array optimizes the power dissipation, conversion rate, inter-stage gain errors, and charge injection. The resulting converter achieves high speed operation with minimal power dissipation.