Sivakumar Makineni

Scalar hardware for performing SIMD operations

Apparatus and method for performing variable precision floating point rounding operations

Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages

Efficient combined array for 2n bit n bit multiplications

Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations

Method, apparatus and computer system for directly transferring and translating data between an integer processing unit and a floating point processing unit

Exception reporting architecture for SIMD-FP instructions

Apparatus for bypassing intermediate results from a pipelined floating point unit to multiple successive instructions

Reduced-hardware soft error detection

Emulating agent and method for reformatting computer instructions into a standard uniform format