Sivananda K. Kanakasabapathy

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at Ioff = 300 pA/µm, VDD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

22 nm technology compatible fully functional 0.1 μm 2 6T-SRAM cell

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the worlds smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)

We have demonstrated a robust magnetic tunnel junction (MTJ) with a resistance-area product RA=8 Omega-mum2 that simultaneously satisfies the statistical requirements of high tunneling magnetoresistance TMR > 15sigma(Rp), write threshold spread sigma(Vw)/<Vw> <7.1%, breakdown-to-write voltage margin over 0.5 V, read-induced disturbance rate below 10-9, and sufficient write endurance, and is free of unwanted write-induced magnetic reversal. The statistics suggest that a 64 Mb chip at the 90-nm node is feasible.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

We present UTBB devices with a gate length (L<inf>G</inf>) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (V<inf>bb</inf>) enables V<inf>t</inf> modulation of more than 125mV with a V<inf>bb</inf> of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-V<inf>t</inf> and power management applications. We explore the impact of GP, BOX thickness and V<inf>bb</inf> on local V<inf>t</inf> variability for the first time. Excellent A<inf>Vt</inf> of 1.27 mV·µm is achieved. We also present simulations results that suggest UTBB has improved scalability, reduced gate leakage (I<inf>g</inf>) and lower external resistance (R<inf>ext</inf>), thanks to a thicker inversion gate dielectric (T<inf>inv</inf>) and body (T<inf>si</inf>) thickness.

Two-level BEOL processing for rapid iteration in MRAM development

The implementation of magnetic random access memory (MRAM) hinges on complex magnetic film stacks and several critical steps in back-end-of-line (BEOL) processing. Although intended for use in conjunction with silicon CMOS front-end device drivers, MRAM performance is not limited by CMOS technology. We report here on a novel test site design and an associated thin-film process integration scheme which permit relatively inexpensive, rapid characterization of the critical elements in MRAM device fabrication. The test site design incorporates circuitry consistent with the use of a large-area planar base electrode to enable a processing scheme with only two photomask levels. The thin-film process integration scheme is a modification of standard BEOL processing to accommodate temperature-sensitive magnetic tunnel junctions (MTJs) and poor-shear-strength magnetic film interfaces. Completed test site wafers are testable with high-speed probing techniques, permitting characterization of large numbers of MTJs for statistically significant analyses. The approach described in this paper provides an inexpensive means for rapidly iterating on MRAM development alternatives to converage on an implementation suitable for a production environment.

Extremely thin SOI (ETSOI) technology: Past, present, and future

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

We report, for the first time, high performance Ultra-thin Body and Box (UTBB) FDSOI devices with a gate length (L_G) of 20nm and BOX thickness (T_BOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (I_eff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (I_off) of 100nA/μm and V_dd of 0.9V. Excellent electrostatics is obtained, demonstrating the scalability of these devices to14nm and beyond. Very low A_Vt (1.3mV·μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device and evidence of continued scalability beyond 14nm is provided.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2].