Smita Jha

Defect reduction in epitaxial GaSb grown on nanopatterned GaAs substrates using full wafer block copolymer lithography

Defect reduction in the large lattice mismatched system of GaSb on GaAs, ∼7%, was accomplished using full wafer block copolymer (BCP) lithography. A self-assembled BCP mask layer was used to generate a hexagonal pattern of ∼20 nm holes on ∼40 nm centers in a 20 nm SiO2 layer. GaSb growth initially takes place selectively within these holes leading to a dense array of small, strain-relaxed epitaxial GaSb islands. The GaSb grown on the patterned SiO2 layer exhibits a reduction in the x-ray linewidth attributed to a decrease in the threading dislocation density when compared to blanket pseudomorphic film growth.

Growth of size and density controlled GaAs/InxGa1−xAs/GaAs (x=0.10) nanowires on anodic alumina membrane-assisted etching of nanopatterned GaAs

Electrochemical anodization using anodic alumina membrane-assisted etching of GaAs(111)B produced nanopatterned GaAs surfaces, which served as substrates for the growth of GaAs/InxGa1−xAs/GaAs quantum well (QW) nanowires with controllable size and density. The nanodepressions created on the anodized GaAs surface minimize the migration of Au nanodots during thermal annealing. The Au nanodots were used in vapor-liquid-solid based growth of the nanostructures. The thickness of the evaporated Au islands, the anodization voltage, and the duration of the etching are the most important parameters used to tailor the size distribution and density of the Au catalysts and hence the diameter of nanowires. Transmission electron microscopy (TEM) reveals that the QW nanowires are single crystals with the ⟨111⟩ main axis direction, similar to nanowires synthesized using conventional methods on bare GaAs substrates and other patterning mechanisms. Z-contrast high-angle annular dark-field scanning TEM confirmed the presenc...

Defect reduction in large lattice mismatch epitaxial growth through block copolymer full wafer patterning

The introduction of defects during the growth of large lattice mismatched III–V materials typically occurs through the injection of 60° dislocations from the surface of the film or islands once a critical thickness or size has been reached. The threading segments from these dislocations lead to electrically active states which deteriorate device performance. Strain relaxation at the earliest stages of growth allows for the development of misfit arrays without the addition of threading segment. Forming and strain relieving small islands can be achieved by intentional patterning as long as the lateral length scale is on the order of the solid state diffusion length. Self-assembly method can be used to produce dense arrays of quantum dots. However, these arrays often develop a multi-modal size distribution as growth proceeds, and the initially pseudomorphic quantum dots evolve into relaxed islands, resulting in a loss of control of the island size and spatial distributions. Large islands form complex defect structures containing a high density of threading dislocations. External patterning on a nanoscale can provide control over island size and placement. Selective epitaxy can constrain the growing epitaxial material to within the patterned mask openings. Once relaxation occurs, the film growth process continues through island coalescence. Patterning at the required length scale and densities (mask openings of ∼20 nm on a 40 nm pitch) would need e-beam lithography, a slow and time-demanding process.

Dislocation reduction in CdTe epilayers grown on silicon substrates using buffered nanostructures

High performance HgCdTe IR detector fabrication on silicon substrates first requires low defect density CdTe buffer layers to be grown on silicon. The objective of this paper is to demonstrate dislocation reduction in CdTe epitaxial layers grown on silicon substrate by using intermediate nanocrystalline CdTe buffer layers. Colloidal synthesis of high quality CdTe nanocrystals was accomplished and spin coating of these CdTe nanocrystals as buffer layers on silicon substrates was carried out. CdTe layers were grown on these buffered substrates by metalorganic chemical vapor deposition (MOCVD). However, the incomplete removal of SiO2 on silicon substrate (by chemical treatment) prevented the exact orientation of the nanocrystals with the silicon substrate and over layer growth of continuous single crystal CdTe epitaxial film. Two new approaches were further investigated: (i) First a thin film of Ge was grown on Si, followed by the deposition of thin SiO2 followed by nanopatterning using block co-polymer (BCP) lithography. Transmission electron microscopy (TEM) showed defect reduction in the CdTe layers grown on these substrates, but the x-ray rocking curves over a larger area gave wider full width half maximum values compared to that of layers grown on blanket surfaces. This was attributed to non uniform nanopatterning in these initial studies; (ii) SiO2 coated silicon substrates were nanopatterned using interference lithography with a honeycomb array of holes. These substrates will be used for the selective growth of germanium and CdTe by MOCVD.

InAs growth on submicron (100) SOI islands for InAs-Si composite channel MOSFETs

In this study, we explore the growth of ultrathin and highly-mismatched InAs directly on SOI islands. SOI islands allow the termination of misfit dislocations at the island edges to relieve the strain. For MOSFETs, the ability to tailor the ratio of InAs to Si in an ultrathin (~3 nm) channel allows optimization of both the channel density-of-states effective mass and the bandgap, for achieving high channel current at low voltage. We show that flat, planar, growth of InAs can be achieved, despite the 11.6% lattice mismatch, on submicron SOI islands by molecular beam epitaxy (MBE) toward realization of MOSFETs. Furthermore, metalorganic chemical vapor deposition is shown to nucleate InAs selectively on SOI islands and first back-gated transistor results are presented.