Soichi Shigeta

Queue processor architecture for novel queue computing paradigm based on produced order scheme

This work proposes a novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a FIFO queue registers instead of random access registers. Datum is inserted in the queue in produced order scheme and can be reused. We show that this feature has a profound implication in the areas of parallel execution, programs compactness, hardware simplicity and high execution speed. Our preliminary performance evaluations have shown a significant performance improvement (e.g., 10% to 26% decrease in program size and 6% to 46% decrease in execution time over a range of benchmark programs) when compared with the earlier proposed architecture.

On the design of a register queue based processor architecture (FaRM-rq)

We propose in this paper a processor architecture that supports multi instructions set through run time functional assignment algorithm (RUNFA). The above processor, which is named Functional Assignment Register Microprocessor (FaRM-rq) supports queue and register based instruction set architecture and functions into different modes: (1) R-mode (FRM) - when switched for register based instructions support, and (2) Q-mode (FQM) - when switched for Queue based instructions support. The entities share a common data path and may operate independently though not in parallel. In FRM mode, the machines shared storage unit (SSU) behaves as a conventional register file. However, in FQM mode, the system organizes the SSU access as a first-in-first-out latches, thus accesses concentrate around a small window and the addressing of registers is implicit trough the Queue head and tail pointers. First, we present the novel aspects of the FaRM-rq1 architecture. Then, we give the novel FQM fundamentals and the principles underlying the architecture.