Somesh Kumar

Analytical Model for Inverter Design Using Floating Gate Graphene Field Effect Transistors

With device dimensions reaching their physical limits, there has been a tremendous focus on development of post CMOS technologies. Carbon based transistors, including graphene and carbon nanotubes, are seen as potential candidates to replace traditional CMOS devices. In that, floating gate graphene field effect transistors (F-GFETs) are preferred over dual gate graphene field effect transistors (D-GFETs) due to their ability to provide variable threshold voltage using a single power supply. In this paper, we present a novel analytical model for the design of a complementary inverter using floating gate bilayer graphene field-effect transistors (F-GFETs). Our proposed model describes the i-v characteristics of the F-GFET for all the regions of operation considering both hole and electron conduction. The i-v characteristics obtained using our model are compared with that of D-GFETs. Based on our proposed model, we obtain the transfer characteristics of a complementary inverter using F-GFETs. Our proposed inverter gives better transfer characteristics when compared with previously reported inverters using either F-GFET or chemically doped D-GFETs.

Design of low power, high gain LNA for WCDMA range and parameters extraction using Artificial Neural Network (ANN)

With the demand of 3G wireless network access is increasing, high performance Wide Band Code Division Multiple Access (WCDMA) transceivers are needed. Low Noise Amplifier (LNA) is the key component of WCDMA transceivers. In this paper, we designed the various configurations of LNA (Single-ended LNA, Differential LNA, Current-reuse LNA) at 180nm technology and compared their performance metrics. The LNA is designed for low power, high gain applications and it provides a series of good performance in Noise Fig. (NF), Linearity, Power consumption and Fig. of merit (FOM). Our analysis shows that Current-reuse LNA (CRLNA) achieve the best gain and FOM among all the other configurations. The FOM of CRLNA is 1.5507GHz/mW which is higher than others LNA configurations. Further, we proposed a novel endeavor in the form of an Artificial Neural Network (ANN) model which estimates different amplifier parameters based upon the simulated results, thereby, providing an alternative to the popular simulation tools which are based on complex analytical and mathematical models and are time consuming.

Design space exploration of nanoscale interconnects with rough surfaces

This paper investigates the effect of surface roughness on interconnect parasitics (RLC per unit length) and performance metrics, such as delay, energy-delay product, bandwidth density, insertion loss and attenuation coefficient of nanoscale on-chip interconnects using 3D EM solver. Our analysis focuses on two industry relevant technology nodes i.e. 13.7 nm and 22 nm. We observe that there is a severe penalty on the performance of interconnects due to surface roughness when analyzed over broadband frequencies. Mandelbrot-Weierstrass (MW) function is used here to define the rough surface profile and the data points obtained from the plot of M-W function are directly used in HFSS for the development of rough conductor interconnect structure. We also present the computational overhead incurred during simulation of rough interconnects.

Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnects with Rough Surfaces

Planar copper interconnects suffer from surface roughness that results in performance degradation. This paper presents a novel analytical model for calculation effective resistivity and mean free path in on-chip copper interconnects. The closed form expressions are obtained from a generalized surface and grain boundary scattering approach that is combined with Mandelbrot-Weierstrass (MW) fractal function. It is observed that resistivity increases while mean free path reduces significantly for rough on-chip interconnects when compared with that of smooth lines. Current and future technology nodes i.e., 45 nm, 22 nm, 13 nm and 7 nm are considered for our analysis. The analytical models are validated against industry standard field solvers Ansys Q3D Extractor and previous data available in literature that exhibit excellent accuracy. Finally, we also present computational overhead in terms of simulation time, matrix size, number of tetrahedrons and memory for different values of roughness and technology nodes.

Investigating the role of interconnect surface roughness towards the design of power-aware network on chip

High-speed metal interconnects play a significant role in the on-chip network system as the network performance largely depends on the behaviour of these interconnects. Variability in wire properties due to the surface roughness directly impacts the overall system performance. In this study, the authors evaluate the effects of interconnect surface roughness on deeply scaled on-chip interconnects (i.e. 22, 13, and 7 nm) in the context of the network on chip (NoC). The critical roughness parameters of interconnect in NoC are extracted by atomic force microscopy analysis of fabricated thin sheets of copper. Their analysis shows that in a 5 × 5 NoC with 25 cores on 2.5 mm × 2.5 mm die, rough interconnects can lead to a significant penalty on energy budget, bandwidth density, bit error rate, the figure of merit and total system throughput. Their analysis shows that this penalty is further increased by moving towards interconnection lines at advanced technology nodes. They simulate the bodytrack workload of PARSEC benchmark by using Tejas Simulator to show the penalty on latency and energy of the architecture due to the rough interconnects. Their study makes an attempt to qualitatively and quantitative highlight the impact of the interconnect surface roughness on the design of power-aware NoCs.

Analytical Modeling and Performance Benchmarking of On-Chip Interconnects with Rough Surfaces

In planar on-chip copper interconnects, conductor losses due to surface roughness demands explicit consideration for accurate modeling of their performance metrics. This is quite pertinent for high-performance manycore processors/servers, where on-chip interconnects are increasingly emerging as one of the key performance bottlenecks. This paper presents a novel analytical model for parameter extraction in current and future on-chip interconnects. Our proposed model aids in analyzing the impact of spatial and vertical surface roughness on their electrical performance. Our analysis clearly depicts that as the technology nodes scale down; the effect of the surface roughness becomes dominant and cannot be ignored. Based on AFM images of fabricated ultra-thin copper sheets, we have extracted roughness parameters to define realistic surface profiles using the well-known Mandelbrot-Weierstrass (MW) fractal function. For our analysis, we have considered four current and future interconnect technology nodes (i.e., 45, 22, 13, 7 nm) and evaluated the impact of surface roughness on typical performance metrics, such as delay, energy, and bandwidth. Results obtained using our model are verified by comparing with industry standard field solver Ansys HFSS as well as available experimental data that exhibits accuracy within 9 percent. We present signal integrity analysis using the eye diagram at 1, 5, 10, and 18 Gbps bit rates to find the increase in frequency dependent losses due to surface roughness. Finally, simulating a standard three line on-chip interconnect structure, we also report the computational overhead incurred for different values of roughness and technology nodes.

Performance modeling and broadband characterization of chip-to-chip interconnects with rough surfaces

Planar copper interconnects suffer from surface roughness that results in their performance degradation. In this paper, we investigate the role of rough conductor surfaces on the electrical performance of chip-to-chip interconnects using 3D full wave simulation. Various interconnect performance metrics, such as delay, energy-delay product, bandwidth density, insertion loss and signal attenuation are evaluated over broadband frequencies. Our results show that rough conductor surfaces can significantly influence these metrics. In that, the maximum penalty on insertion loss, attenuation, delay, energy-delay product and bandwidth density is 50%, 86%, 3X, 3.7X and 28%, respectively. Finally, we report the computational overhead for simulating high-speed interconnects with rough surfaces.

A high-k, metal gate vertical-slit FET for ultra-low power and high-speed applications

In this paper, we propose a novel Vertical-Slit Field Effect Transistor (VeSFET) with high-k gate dielectrics and metallic gates with different work function (Φm). The gate dielectric material and gate electrodes in traditional VeSFETs are replaced by high-k dielectrics and metals, respectively. We investigate the effect of these on the electrical characteristics of our proposed device. Various performance parameters such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), Threshold Voltage (VT), leakage power (Poff), propagation delay, Ion/Ioff ratio are obtained using exhaustive TCAD simulations and compared with that of conventional VeSFETs. Our analysis shows that the proposed high-k metal gate VeSFET exhibits higher Ion/Ioff ratio, lower leakage current, lower leakage power, lower delay with near ideal SS and minimum DIBL. Also, our proposed device exhibits higher on-current. This makes it a potential candidate for ultra-low power, high-speed applications with reduced short channel effects. To illustrate the benefits of our proposed device, we design a complementary inverter using the proposed high-k metal VeSFETs. Our analysis clearly highlights the improvement in delay and power dissipation obtained using the proposed structure when compared to that using conventional VeSFETs.

Design space exploration of Through Silicon Vias for high-speed, low loss vertical links

In this paper, performance analysis of Through Silicon Vias (TSVs) considering various bonding techniques is investigated. In that, bonding of TSVs using Cu-Sn microbumps, Cu-Ag microbumps and Cu-Cu direct bonding is considered. We present SPICE-compatible equivalent circuits for these configurations using exhaustive simulations performed on electromagnetic field solver, Ansys Q3D. We analyze these TSV configurations for various interconnect performance metrics, such as delay, energy delay product, energy per bit, insertion loss and bandwidth density. Our analysis gives physical insights into the effect of microbumps/discontinuities on the TSV performance. Our analytical results show that vertical interconnects using Cu-Cu direct bonding significantly outperforms those using Cu-Ag or Cu-Sn microbumps, which makes it an excellent candidate for high-speed, low loss vertical links.