Song Bian

Nonlinear delay-table approach for full-chip NBTI degradation prediction

As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. Hence, taking aging-induced degradation into account during the design phase can greatly improve the reliability of the manufactured devices. However, considering instance-dependent Vth degradations for extremely large circuits, like processors, is time-consuming. In this research, we focus on the negative bias temperature instability (NBTI) as the aging-induced degradation mechanism, and propose a fast and efficient way of estimating NBTI-induced delay degradation by utilizing static-timing analysis (STA) and simulation-based lookup table (LUT). Probability-based delay model (PBDM) for each gate is characterized in advance, having input slews, output capacitances and signal probabilities as the table indices. Using the PBDM modeled, path delays of arbitrary circuits can be efficiently estimated. With a typical five-stage pipelined processor as the design target, by comparing the calculated delay from LUT with the reference delay calculated by a commercial circuit simulator, we achieved 4114 times speedup within 5.6% delay error.

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

Negative bias temperature instability (NBTI) has become one of the major reliability concerns for nanoscale CMOS technology. The NBTI effect degrades pMOS transistors by stressing them with negatively biased voltage, while the transistors heal themselves as the negative bias is removed. In this paper, we propose a cross-layer mitigation technique for NBTI-induced timing degradation in processors. The NOP (No Operation) instruction is replaced by a custom NOP instruction for healing purpose. Cells that are likely to be stressed under negative bias are classified and their upstream cell will be replaced by the internal node control (INC) logics. Upon encountering a custom NOP instruction, the INC logics will force the NBTI-stressed cell to be in its healing mode. The optimal INC logic insertion through genetic programming approach achieves much greater delay mitigation of 44.3% than prior works in a 10-year span with less than 4% of power and negligible area overhead.

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation

As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) is known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, with careful examination, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and proposes a two-stage path extraction algorithm to identify the invariable critical paths in the processor. Through numerical experiment on a MIPS32 processor, we performed a detailed signal probability analysis, and successfully extracted 85 invariable critical paths out of the 24,978 path candidates, achieving nearly 300× reduction in the sheer number of paths.

DWE: decrypting learning with errors with errors

The Learning with Errors (LWE) problem is a novel foundation of a variety of cryptographic applications, including quantumly-secure public-key encryption, digital signature, and fully homomorphic encryption. In this work, we propose an approximate decryption technique for LWE-based cryptosystems. Based on the fact that the decryption process for such systems is inherently approximate, we apply hardware-based approximate computing techniques. Rigorous experiments have shown that the proposed technique simultaneously achieved 1.3× (resp., 2.5×) speed increase, 2.06× (resp., 7.89×) area reduction, 20.5% (resp., 4×) of power reduction, and an average of 27.1% (resp., 65.6%) ciphertext size reduction for public-key encryption scheme (resp., a state-of-the-art fully homomorphic encryption scheme).

Comparative study of path selection and objective function in replacing NBTI mitigation logic

Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. Various INC replacement algorithms have been proposed, but there are no evaluations for the necessity of the signal probability update and the aged delay calculation during optimization, which are highly CPU intensive. Also, the mitigation effectiveness and optimization time have not been fully evaluated. In this paper, strategies for selecting replacement candidates and the objective functions in optimization are evaluated using an example processor design. From the experimental result, it is found that the recalculation of the signal probability and the aged path delay greatly improves the optimization results. It is also found that the evaluated path limitation through path clustering with the average objective function reduces calculation time, without degrading the mitigation gain.

SCAM: Secured content addressable memory based on homomorphic encryption

We propose an implementation of a secured content addressable memory (SCAM) based on homomorphic encryption (HE), where HE is used to compute the word matching function without the processor knowing what is being searched and the result of matching. By exploiting the shallow logic structure (XNOR followed by AND) of content addressable memory (CAM), we show that SCAM can be implemented with only additive homomorphism, greatly improving the efficiency of the HE algorithm. In the proposed method, the logic of homomorphic XNOR-AND is replaced with homomorphic XOR-OR, requiring only simple additions to be performed on the ciphertext. We also show that our scheme can be implemented by highly parallelizable and simple hardware architecture. Through experiment, we demonstrate that our software implementation is already 403x faster than the fastest known algorithm. With the help of hardware, we can achieve an energy reduction per word match by a factor of 477 million times, making our SCAM scheme much more practical.