Songang Peng

The anistropy of field effect mobility of CVD graphene grown on copper foil.

Through adjusting the focal plane of the optical microscope, we have verifi ed that these trenches on the copper foil have a con-cave cross section. It is similar with the surface topography of copper foil, whose optical image is shown in the inset panel of Figure 1 a. The surface of copper foil shows a directional texture consisting of many parallel trenches with spacing on the order of micrometers, these trenches are considered to be produced during the foil rolling process used to fabricate the Cu foil, with the trenches running parallel to the shear/drawing direction.

Heavily p-type doped chemical vapor deposition graphene field-effect transistor with current saturation

Current saturation in graphene field-effect transistor (GFET) is of significant importance to improve the maximum oscillation frequency (fmax). We investigated the direct current (dc) and radio frequency (rf) characteristics of a heavily p-type doped GFET based on chemical vapor deposition grown material. The drain current saturation is found in our device. It cannot be explained by the “pinch-off” effect associated with ambipolar transport, but can be attributed to nonlinear channel conductance and velocity saturation in unipolar channel. This study promotes understanding the behaviors of heavily doped GFETs and their radio frequency applications.

Carrier-Number-Fluctuation Induced Ultralow 1/f Noise Level in Top-Gated Graphene Field Effect Transistor

A top-gated graphene FET with an ultralow 1/f noise level of 1.8 × 10-12 μm2Hz1- (f = 10 Hz) has been fabricated. The noise has the least value at Dirac point, it then increases fast when the current deviates from that at Dirac point, the noise slightly decreases at large current. The phenomenon can be understood by the carrier-number-fluctuation induced low frequency noise, which caused by the trapping-detrapping processes of the carriers. Further analysis suggests that the effect trap density depends on the location of Fermi level in graphene channel. The study has provided guidance for suppressing the 1/f noise in graphene-based applications.

Abnormal Dirac point shift in graphene field-effect transistors

The shift of Dirac point in graphene devices is of great importance, influencing the reliability and stability. Previous studies show the Dirac point shifts slightly to be more positive when the drain bias increases. Here, an abnormal shift of Dirac point is observed in monolayer graphene field effect transistors by investigating the transfer curves under various drain biases. The voltage of Dirac point shifts positively at first and then decreases rapidly when the channel electric field exceeds some threshold. The negative Dirac point shift is attributed to holes injection into oxide layer and captured by the oxide traps under high channel electric field. This can also be demonstrated through a simple probability model and the graphene Raman spectra before and after the DC measurement.

Effect of source-gate spacing on direct current and radio frequency characteristic of graphene field effect transistor

The effect of source-gate spacing on graphene filed effect transistors has been investigated. Reducing the source gate spacing allows for a significant improvement on both the direct current and radio frequency (RF) performances. Instead of the generally considered output conductance, our results suggest that the access resistances at the un-gated region contribute more to the maximum oscillation frequency (fmax). Further analysis reveals that the ratio of cut off frequency (fT) to fmax is also sensitive to the resistances at source-gate spacing. This work can be used to guide the further optimization of graphene-based RF devices.

Depressed scattering across grain boundaries in single crystal graphene

We investigated the electrical and quantum properties of single-crystal graphene (SCG) synthesized by chemical vapor deposition (CVD). Quantum Hall effect and Shubnikov de Hass oscillation, a distinguishing feature of a 2-dimensional electronic material system, were observed during the low temperature transport measurements. Decreased scattering from grain boundaries in SCG was proven through extracting information from weak localization theory. Our results facilitate understanding the electrical properties of SCG grown by CVD and its applications in high speed transistor and quantum devices.

Growth promotion of vertical graphene on SiO2/Si by Ar plasma process in plasma-enhanced chemical vapor deposition

This study investigates the growth promotion of vertically oriented graphene in plasma-enhanced chemical vapor deposition through Ar plasma treatment. Combined with various substrate treatments, including hydrofluoric acid etching and oxidation after Ar plasma treatment, Ar plasma pretreatment promotes vertical growth through the microcavity on the rough substrate surface and the active growth sites. The microcavity affects the strain distribution and defects of as-deposited planar films, which benefit the transition of 2D deposition to 3D vertical growth. A growth model on the effect of Ar plasma pretreatment is proposed.

Towards a cleaner graphene surface in graphene field effect transistor via N,N-Dimethylacetamide

Graphene is a two-dimensional material with a high surface to volume ratio and the fabrication process of graphene field effect transistors always introduces unintended contaminates like photoresidues on the surface of graphene. These contaminations are difficult to remove by conventional acetone solvent and suppress the intrinsic properties of graphene. To address the problem, a wet-chemical approach employing N,N-Dimethylacetamide (C4H9NO) was developed in this study, which shows an increase of the carrier mobility and a reduction of minimum conductance point in our devices. Raman spectroscopy and atomic force microscope were carried out to verify the cleaning effect of the approach. Our method provides a simple and effective way to enhance the electrical performance of graphene field effect transistors and can be readily integrated into the CMOS fabrication pilot line.

Intrinsic carrier mobility extraction based on a new quasi-analytical model for graphene field-effect transistors

The most common method of mobility extraction for graphene field-effect transistors is proposed by Kim. Kims method assumes a constant mobility independent of carrier density and gets the mobility by fitting the transfer curves. However, carrier mobility changes with the carrier density, leading to the inaccuracy of Kims method. In our paper, a new and more accurate method is proposed to extract mobility by fitting the output curves at a constant gate voltage. The output curves are fitted using several kinds of current–voltage models. Besides the models in the literature, we present a modified model, which takes into account not only the quantum capacitance, contact resistance, but also a modified drift velocity-field relationship. Comparing with the other models, this new model can fit better with our experimental data. The dependence of carrier intrinsic mobility on carrier density is obtained based on this model.

Depositing aluminum as sacrificial metal to reduce metal–graphene contact resistance*

Reducing the contact resistance without degrading the mobility property is crucial to achieve high-performance graphene field effect transistors. Also, the idea of modifying the graphene surface by etching away the deposited metal provides a new angle to achieve this goal. We exploit this idea by providing a new process method which reduces the contact resistance from 597 Ωμm to sub 200 Ωμm while no degradation of mobility is observed in the devices. This simple process method avoids the drawbacks of uncontrollability, ineffectiveness, and trade-off with mobility which often exist in the previously proposed methods.