Sonja Sioncke

Capacitance-voltage characterization of GaAs–Al2O3 interfaces

The authors apply the conductance method at 25 and 150°C to GaAs–Al2O3 metal-oxide-semiconductor devices in order to derive the interface state distribution (Dit) as a function of energy in the bandgap. The Dit is governed by two large interface state peaks at midgap energies, in agreement with the unified defect model. S-passivation and forming gas annealing reduce the Dit in large parts of the bandgap, mainly close to the valence band, reducing noticeably the room temperature frequency dispersion. However the midgap interface state peaks are not affected by these treatments, such that Fermi level pinning at midgap energies remains.

Characteristic trapping lifetime and capacitance-voltage measurements of GaAs metal-oxide-semiconductor structures

The authors show the implications that the free carrier trapping lifetime has on the capacitance-voltage (CV) characterization method applied to metal-oxide-semiconductor (MOS) structures. It is shown that, whereas the CV characterization method for deducing interface state densities works well for Si, the generally used frequency range of 100Hz–1MHz is much less adapted to GaAs MOS structures. Only interface trapping states in very small portions of the GaAs bandgap are measured with this frequency range, and mainly the very important midgap region is not properly probed. Performing an additional measurement at 150°C on GaAs MOS structures eliminates this problem.

Electrical Properties of III-V/Oxide Interfaces

The great technological achievements of the Silicon Metal-Oxide-Semiconductor (MOS) system were possible because of the very good electrical quality of the Si-SiO2 interface. H-passivation of dangling bonds at the latter interface can result in interface state densities lower than 10 eVcm. As Si CMOS scaling now slowly approaches the atomic length scale, an extension of the technology roadmap might be possible by replacing the Si with alternative substrates with higher mobility. For nMOS, III-V materials seem to be good candidates, because of their high electron mobility. Unfortunately, III-V/oxide interfaces are not quite as robust as the Si-SiO2 interface and most interfaces present high densities of interface states. In the present contribution we analyze GaAs and InGaAs interfaces. Several characterization methods such as the photoluminescence intensity method and the conductance method at high and /or low substrate temperatures are used to characterize the interface state distribution of several III-V interfaces. The interface state distributions of GaAs and In0.53Ga0.47As interfaces with amorphous high-k oxides are presented. These distributions are, as opposed to Si, characterized by localized peaks in the bandgap, which leads to some difficulties for the different characterization techniques. For GaAs, all amorphous oxide interfaces show two very large and localized peaks at around mid-gap energies. Whereas the interface state density closer to the band edges can be reduced with (NH4)2S-cleaning and Hpassivation, the large mid-gap peaks can not be successfully suppressed using these techniques. As a consequence GaAs-amorphous oxide interfaces can not be inverted. For In0.53Ga0.47As, the interface states show a very asymmetric distribution, with reasonably low density close to the conduction band and a very strong increase of interface state density towards the valence band (Figure 1). The consequences of this distribution are discussed in terms of band bending coupling ratio, the ability to control the band bending at the oxide-semiconductor interface, and the performance of the corresponding nMOSFET devices.

Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

To address the integration of the high-mobility Ge/III-V MOSFET, a common gate stack (CGS) solution is proposed for the first time and demonstrated on Ge and InGaAs channels with combined hole and electron field-effect mobility values up to 400cm2/eV-s and 1300cm2/eV-s. Based on the duality found on the InGaAs/Ge MOS system, this approach aims to integrate the InGaAs/Ge MOSFET processes for high performance CMOS applications with an emphasis on progressive EOT scaling.

Capacitance–Voltage Characterization of GaAs–Oxide Interfaces

We will shortly review the basic physics of charge-carrier trapping and emission from trapping states within the bandgap of a semiconductor in order to show that high-temperature capacitance-voltage (C-V) measurements are necessary for GaAs metal-oxide-semiconductor characterization. The midgap trapping states in GaAs have characteristic emission times on the order of 1000 s, which makes them extremely complicated to measure at room temperature. Higher substrate temperatures speed up these emission times, which makes measurements of the midgap traps possible with standard C-V measurements. C-V characterizations of GaAs/Al 2 O 3 , GaAs/Gd 2 O 3 , GaAs/HfO 2 , and In 0.15 Ga 0.85 As/Al 2 O 3 interfaces show the existence of four interface state peaks, independent of the gate oxide deposited: a hole trap peak close to the valence band, a hole trap peak close to midgap energies, an electron trap peak close to midgap energies, and an electron trap peak close to the conduction band.

Reaction mechanisms for atomic layer deposition of aluminum oxide on semiconductor substrates

In this work, we have studied the TMA/H2O (TMA = Al(CH3)3) atomic layer deposition (ALD) of Al2O3 on hydroxyl (OH) and thiol (SH) terminated semiconductor substrates. Total reflection x-ray fluorescence reveals a complex growth-per-cycle evolution during the early ALD reaction cycles. OH and SH terminated surfaces demonstrate growth inhibition from the second reaction cycle on. Theoretical calculations, based on density functional theory, are performed on cluster models to investigate the first TMA/H2O reaction cycle. Based on the theoretical results, we discuss possible mechanisms for the growth inhibition from the second reaction cycle on. In addition, our calculations show that AlCH3 groups are hydrolyzed by a H2O molecule adsorbed on a neighboring Al atom, independent of the type of backbonds (Si-O, Ge-O, or Ge-S) of AlCH3. The coordination of Al remains four-fold after the first TMA/H2O reaction cycle.

Atomic Layer Deposition of Hafnium Oxide on Ge and GaAs Substrates: Precursors and Surface Preparation

To increase complementary metal oxide semiconductor (CMOS) device performance, new materials are introduced in the gate stack (high-k dielectrics and metal gates) and the transistor channel (Ge, III-V materials). In this work we study the atomic layer deposition (ALD) of hafnium oxide on Ge and GaAs substrates. Passivation layers are required to achieve a sufficiently low interface state density, but these might also influence the growth behavior and dielectric quality. Therefore, we investigate the effect of surface preparation, for example, native oxide, wet clean, thermal oxidation, and S-passivation, for the HfCl 4 /H 2 O and tetrakis diethylamino hafnium = ((C 2 H 5 ) 2 N) 4 Hf (TDEAH)/H 2 O processes. The growth of HfO 2 from initial submonolayer coverage to continuous HfO 2 film is studied by means of Rutherford backscattering, static time-of-flight secondary ion mass spectroscopy, and X-ray photoelectron spectroscopy. HfCl 4 /H 2 O ALD depends on the surface preparation. The growth is enhanced on oxide surfaces (thermally grown GeO 2 , HF-cleaned Ge, and GaO x -ASO y ) and inhibited on oxide-free substrates (HBr-cleaned Ge). The initial island growth regime is least pronounced on germanium oxide. In contrast, TDEAH/H 2 O ALD is independent of the surface preparation. The growth is inhibited in the first ∼20 cycles on native oxide and S-passivated GaAs [(NH 4 ) 2 S treatment], but the initial island growth regime is quickly followed by the two-dimensional growth regime.

Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO 2 /HfO 2 pMOSFETs and implications for the screening of alternative high-mobility substrate/dielectric CMOS gate stacks

We study charge trapping in a variety of Ge-based pMOS and nMOS technologies, either with Si passivation and conventional SiO2/HfO2 gate stack, or with GeOx/high-k gate stacks. A general model for understanding this phenomenon in alternative substrate/dielectric systems is proposed. We discuss two different approaches to pursue a reduction of charge trapping in alternative material systems, which will be necessary for achieving reliable high-mobility devices.

Optical activity effects in second harmonic generation from anisotropic chiral thin films

Circular-difference effects in second-harmonic generation have been used to study chiral, anisotropic thin films of a helicene derivative. For such samples, these effects arise both from the chirality of the film and from its anisotropy. We show theoretically and experimentally that there is a fundamental difference between a circular-difference effect originating from chirality and anisotropy. A method is described that distinguishes the two contributions.

Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

High-Mobility n-MOSFET options with Ge and InGaAs channels are of intense interests. As the well-known interfacial trap (Dit) problem appears now contained, new challenges are emerging from above the interface. The evidence of oxide border traps (BT) in high-k dielectrics and its effect on the on-state performance of Ge and InGaAs n-MOSFETs are presented in this study through combined trap and transport analyses. The impact of the oxide traps on device frequency response and threshold voltage (Vth) stability could challenge the commercial realization of the high mobility channel MOSFET.