Soo-ho Park

P-97: Analysis of Wall-Voltage Variation During Address Period Using V(t) Closed Curves

To explain a non-uniformity of the address discharge during an address period, the wall voltage variation during an address period was investigated as a function of the number of the applied address pulse by the Vt closed curve. It was observed that the wall voltage between the scan and address electrodes was decreased with an increase in the number of the applied address pulse. It was also observed that the wall voltage variation during an address period strongly depends on the voltage difference between the Y and A electrodes.

P‐140: A Modified Selective Reset‐Waveform to Minimize Wall‐Voltage Variation During Address‐Period in Full‐HD PDP

This paper proposes a modified selective reset driving waveform that can lower the potential difference between the scan and address electrodes by applying the address-bias voltage (Va-bias) to the address electrode during the application of the rising pulse of Y-electrode in the selective reset-period. This address-bias voltage (Va-bias) plays a role in suppressing the wall-charge accumulation on the address electrode during the selective reset-period, thereby contributing to minimizing the wall-voltage variation during the address-period and as such allowing the higher voltage difference (=ΔVy) between the scan low voltage (Vsl) and the negative falling ramp voltage (Vnf) during an address-period without any misfiring discharge. When adopting the proposed selective reset waveform, the address discharge delay time is observed to be reduced by about 120 ns.

P-95: Distortion of Sustain Waveform Relative to Displayed Area and Its Compensation for Stable Address Discharge in AC-Plasma Display Panel

The sustain waveforms are distorted relative to the displayed area. The distorted sustain waveform, especially the last X sustain waveform causes the address time to be delayed. Accordingly, to produce a stable address discharge irrespective of the displayed area, the sustain waveform, especially the last X sustain waveform prior to the selective reset waveform, is compensated by making its rising slope faster in proportion to the displayed area by means of controlling the timing sequence of the energy recovery circuit (ERC) circuit. As a result, the compensated sustain waveform enables the address delayed time to be saturated irrespective of the displayed area.

18.2: Investigation of Micro-Scale Capillary Plasmas for a PDP Application

The properties and characteristics of micro-scale Capillary Plasma Electrode Discharges (CPEDs) were investigated. We examined the basic discharge characteristics of AC-type micro-scale CPEDs as a function of the L/D ratio. Using the basis of the previous findings, we applied the CPED concept to the design of a commercial plasma display panel and compared the discharge characteristics with those of a conventional DBD-based PDP. The optimum parameters for micro-scale CPED are L/D ratio = ∼0.5, diameter (D) = 125 μm, length (L) = 70 μm, total dielectric thickness (T) = 90 μm. The luminous efficiency of the optimized CPED structure is higher than that of DBD structure with same dielectric thickness. However, by comparison with DBD structure with T= 45 μm which is somewhat higher dielectric thickness than current conventional PDP (T= ∼30 μm) but has almost similar discharge characteristic, there is no noticeable difference in the luminous efficiency.