Soonhak Kwon

A digit-serial multiplier for finite field GF(2/sup m/)

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2/sup m/) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data come in continuously, the proposed array can produce multiplication results at a rate of one every /spl lceil/m/L/spl rceil/ clock cycles, where L is the selected digit size. Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

FPGA implementation of high performance elliptic curve cryptographic processor over GF(2163)

In this paper, we propose a high performance elliptic curve cryptographic processor over GF(2^1^6^3), one of the five binary fields recommended by National Institute of Standards and Technology (NIST) for Elliptic Curve Digital Signature Algorithm (ECDSA). The proposed architecture is based on the Lopez-Dahab elliptic curve point multiplication algorithm and uses Gaussian normal basis for GF(2^1^6^3) field arithmetic. To achieve high throughput rates, we design two new word-level arithmetic units over GF(2^1^6^3) and derive parallelized elliptic curve point doubling and point addition algorithms with uniform addressing based on the Lopez-Dahab method. We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143MHz. Our design is roughly 4.8 times faster with two times increased hardware complexity compared with the previous hardware implementation proposed by Shu et al. Therefore, the proposed elliptic curve cryptographic processor is well suited to elliptic curve cryptosystems requiring high throughput rates such as network processors and web servers.

Efficient tate pairing computation for elliptic curves over binary fields

In this paper, we present a closed formula for the Tate pairing computation for supersingular elliptic curves defined over the binary field

FPGA accelerated tate pairing based cryptosystems over binary fields

\mathbb F_{2^m}

Efficient Linear Array for Multiplication in GF (2 m ) Using a Normal Basis for Elliptic Curve Cryptography

of odd dimension. There are exactly three isomorphism classes of supersingular elliptic curves over

An optimized hardware architecture for the montgomery multiplication algorithm

\mathbb F_{2^m}

Reconfigurable Computing Approach for Tate Pairing Cryptosystems over Binary Fields

for odd m and our result is applicable to all these curves.

A compact and fast division architecture for a finite field GF(2 m )

Tate pairing based cryptosystems have recently emerged as an alternative to traditional public key cryptosystems because of their ability to be used in multi-party identity-based key management schemes. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. Three schemes for Tate pairing computations have been proposed in the literature: cubic elliptic, binary elliptic, and binary hyperelliptic. For our implementation we have chosen the binary elliptic case because of the simple underlying algorithms and efficient binary arithmetic. In this paper, we propose a new FPGA-based architecture of the Tate pairing-based computation over the binary fields F2239 and F 2283. Even though our field sizes are larger than in the architectures based on cubic elliptic curves or binary hyperelliptic curves with the same security strength, nevertheless fewer multiplications in the underlying field need to performed. As a result, the computational latency for a pairing computation has been reduced, and our implementation runs 10-to-20 times faster than the equivalent implementations of other pairing-based schemes at the same level of security strength. At the same time, an improvement in the product of latency by area by a factor between 12 and 46 for an equivalent type of implementation has been achieved

A fast digit-serial systolic multiplier for finite field GF(2/sup m/)

We present a new sequential normal basis multiplier over GF(2 m ). The gate complexity of our multiplier is significantly reduced from that of Agnew et al. and is comparable to that of Reyhani-Masoleh and Hasan, which is the lowest complexity normal basis multiplier of the same kinds. On the other hand, the critical path delay of our multiplier is same to that of Agnew et al. Therefore it is supposed to have a shorter or the same critical path delay to that of Reyhani-Masoleh and Hasan. Moreover our method of using a Gaussian normal basis makes it easy to find a basic multiplication table of normal elements. So one can easily construct a circuit array for large finite fields, GF(2 m ) where m = 163, 233, 283, 409, 571, i.e. the five recommended fields by NIST for elliptic curve cryptography.

Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve

Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koc introduced a now-classical architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency, this architecture performs a single Montgomery multiplication in approximately 2n clock cycles, where n is the size of operands in bits. In this paper we propose and discuss an optimized hardware architecture performing the same operation in approximately n clock cycles with almost the same clock period. Our architecture is based on pre-computing partial results using two possible assumptions regarding the most significant bit of the previous word, and is only marginally more demanding in terms of the circuit area. The new radix-2 architecture can be extended for the case of radix-4, while preserving a factor of two speed-up over the corresponding radix-4 design by Tenca, Todorov, and Koc from CHES 2001. Our architecture has been verified by modeling it in Verilog-HDL, implementing it using Xilinx Virtex-II 6000 FPGA, and experimentally testing it using SRC-6 reconfigurable computer.