Soonwan Chung

High-cycle fatigue life prediction for Pb-free BGA under random vibration loading

This paper develops an assessment methodology based on vibration tests and finite element analysis (FEA) to predict the fatigue life of electronic components under random vibration loading. A specially designed PCB with ball grid array (BGA) packages attached was mounted to the electro-dynamic shaker and was subjected to different vibration excitations at the supports. An event detector monitored the resistance of the daisy chained circuits and recorded the failure time of the electronic components. In addition accelerometers and dynamic signal analyzer were utilized to record the time-history data of both the shaker input and the PCB’s response. The finite element based fatigue life prediction approach consists of two steps: The first step aims at characterizing fatigue properties of the Pb-free solder joint (SAC305/SAC405) by generating the S–N (stress-life) curve. A sinusoidal vibration over a limited frequency band centered at the test vehicle’s 1st natural frequency was applied and the time to failure was recorded. The resulting stress was obtained from the FE model through harmonic analysis in ANSYS. Spectrum analysis specified for random vibration, as the second step, was performed numerically in ANSYS to obtain the response power spectral density (PSD) of the critical solder joint. The volume averaged Von Mises stress PSD was calculated from the FEA results and then was transformed into time-history data through inverse Fourier transform. The rainflow cycle counting was used to estimate cumulative damages of the critical solder joint. The calculated fatigue life based on the rainflow cycle counting results, the S–N curve, and the modified Miner’s rule agreed with actual testing results.

Finite element based fatigue life prediction for electronic components under random vibration loading

This work develops an assessment methodology based on experiments and finite element analysis (FEA) to determine the solder joint fatigue life of electronic components under random vibration loading. Specially designed PCB with Ball Grid Array (BGA) packages attached was mounted to the Electro dynamic shaker and was applied to different random vibration excitations at the supports. Meanwhile, an event detector monitored the resistance of the daisy chained circuits and recorded the failure time of the electronic components. In addition accelerometers and dynamic signal analyzer were utilized to record the time history data of both the shaker input and the PCBs response, and to obtain the transmissibility function of the test vehicles. This finite element based fatigue life prediction approach consists of two steps: The first step aims at characterizing fatigue properties of the solder joint by generating its own S-N (stress-life) curve. A sinusoidal vibration over a limited frequency band centered at the test vehicles 1st natural frequency was applied and the time to failure was recorded. The resulting stress was obtained from the FE model through harmonic analysis in ANSYS. Spectrum analysis specified for random vibration, as the second step, was performed numerically in ANSYS to obtain the response Power Spectral Density (PSD) of the critical solder ball. The volume averaged Von Mises stress PSD was calculated out of the FEA results and then was transformed into time history data through inverse Fourier transform. Rainflow cycle counting was used to estimate cumulative damage of the critical solder joint. The calculated fatigue life based on the Rainflow cycle counting results, the S-N curve, and the modified Miners rule agreed with actual testing results.

Measurement of Transient Dynamic Response of Circuit Boards of a Handheld Device During Drop Using 3D Digital Image Correlation

In this work, a new experimental methodology for analyzing the drop impact response is assessed using a pair of high-speed digital cameras and 3D digital image correlation software. Two different test boards are subjected to Joint Electron Device Engineering Council (JEDEC) standard free-fall impact conditions of half-sine pulse of 1500 G in magnitude and 0.5 ms in duration. The drop is monitored using a pair of synchronized high-speed cameras at a rate of up to 15,000 frames per second. The acquired images are subsequently analyzed to give full-field dynamic deformation, shape, and strain over the entire board during and after impact. To validate this new methodology for analyzing the impact response, the in-plane strain as well as the out-of-plane acceleration at selected locations were measured simultaneously during the drop using strain gauge and accelerometers and were compared with those obtained using high-speed cameras and 3D digital image correlation presented in this paper. Comparison reveals excellent correlation of the transient behavior of the board during impact and confirms the feasibility of using the full-field measurement technique used in this study. DOI: 10.1115/1.3000097

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated

Realistic warpage evaluation of printed board assembly during reflow process

Purpose – This paper aims to develop an estimation tool for warpage behavior of slim printed circuit board (PCB) array while soldering with electronic components by using finite element method. One of the essential requirements for handheld devices, such as smart phone, digital camera, and Note-PC, is the slim design to satisfy the customers’ desires. Accordingly, the printed circuit board (PCB) should be also thinner for a slim appearance, which would result in decreasing the PCB’s bending stiffness. This means that PCB deforms severely during the reflow (soldering) process where the peak temperature goes up to 250°C. Therefore, it is important to estimate PCB deformation at a high temperature for thermo-mechanical quality/reliability after reflow process. Design/methodology/approach – A numerical simulation technique was devised and customized to accurately estimate the behavior of a thin printed board assembly (PBA) during reflow by considering all components, including PCB, microelectronic packages an...

Development of PCB design guide and PCB deformation simulation tool for slim PCB quality and reliability

In this paper, major concerns from the use of slim PCB are considered and several efforts to solve the trouble are introduced. The critical phenomena by the application of slim PCB are large warpage generated during reflow (soldering) process and large deformation of IC package by external impact environment. Those are due to the low bending rigidity according to the decrease of thickness, and increase the SMD process defect and decrease the drop reliability of IC package mounted on PCB. To solve those issues, various experiment and simulation are performed. First, PCB internal layer material to resist high temperature is investigated. To predict large warpage during reflow process, PCB thermo-mechanical simulation tool is also developed. To increase drop reliability of BGA package, robust design guide for drop impact condition is studied. Last, PCB pad surface finish recently developed is introduced to find the possibility to increase solder joint strength. Based on the material, process and reliability approaches, current PCB deformation level for main board is shown and the optimal PCB design for smaller warpage and larger reliability is obtained.

Thermal fatigue reliability for Cu-Pillar bump interconnection in flip chip on module and underfill effects

Purpose – The purpose of this paper is to assess the thermo-mechanical reliability of a solder bump with different underfills, with the evaluation of different underfill materials. As there is more demand in higher input/output, smaller package size and lower cost, a flip chip mounted at the module level of a board is considered. However, bonding large chips (die) to organic module means a larger differential thermal expansion mismatch between the module and the chip. To reduce the thermal stresses and strains at solder joints, a polymer underfill is added to fill the cavity between the chip and the module. This procedure has typically, at least, resulted in an increase of the thermal fatigue life by a factor of ten, as compared to the non-underfilled case. Yet, this particular case is to deal with a flip chip mounted on both sides of a printed circuit board (PCB) module symmetrically (solder bump interconnection with Cu-Pillar). Note that Cu-Pillar bumping is known to possess good electrical properties a...

Interfacial reliability between hot-melt polyamides resin and textile for wearable electronics application

Abstract The interfacial reliability between hot-melt polyamides resin and textile is studied to investigate whether hot-melt polyamides resin is useful as an encapsulation material of wearable electronic devices. Four kinds of hot-melt polyamides resins and six kinds of textile fabrics are used, and the test sample is fabricated by molding polyamides resin on top of textile. To confirm the mechanical reliability between polyamides resin and textile under water washing and dry cleaning condition, the adhesion strength is measured by 90° peel test not only at initial state but also after exposing the sample to moisture and heat. As a result, it can be seen after high temperature and humidity test that peel strength is degraded and fracture mode can be changed from adhesive failure to cohesive failure according to textile fabric. Also, the optimal combination of polyamides resin and textile for better peel strength is obtained.

Effect of Shield-Can Design on Dynamic Responses of PCB Under Board Level Drop Impact

When a handheld device is subjected to a drop impact, the out-of-plane deformation of printed circuit board (PCB) is a major concern to manufacturers as it is directly proportional to the stress which causes failure for the solder joints. The shield-can attached to the PCB can provide additional mechanical strength and minimize the out-of-plane deformation. In this work, board level drop test is conducted with instrumentation following the Joint Electron Device Engineering Council (JEDEC) test standards. A non-contact full field optical measurement technique, Digital Image Correlation (DIC), is applied to monitor and document the dynamic responses of PCB during the drop test. Different shield-can type varying in shape and size are attached to the PCB through frame or clip type connection. The effects of these two connecting methods, as well as the shape and size of shield-can, on the dynamic responses of PCB are analyzed experimentally. Along with board level drop experiments, a detailed 3D FEA model has been developed to verify and analyze the dynamic responses of PCB using ANSYS/LS-DYNATM. Several simulations have been performed to verify experimental results. Different contact techniques, such as Nodes merge and Tied Nodes to Surface (TDNS) contact have been applied as boundary conditions to connect shield-can with PCB and a proper representation of connection is found in the simulation.Copyright

Comparative Studies on Solder Joint Reliability of Plastic and Ceramic Ball Grid Array Packages of the Same Form Factor Under Power and Accelerated Thermal Cycling

Experimental and numerical techniques are employed to assess the thermomechanical behavior of ceramic and organic flip chip packages under power cycling (PC) and accelerated thermal cycling (ATC). In PC, nonuniform temperature distribution and different coefficients of thermal expansion of each component make the package deform differently compared to the case of ATC. Traditionally, reliability assessment is conducted by ATC because ATC is believed to have a more severe thermal loading condition compared to PC, which is similar to the actual field condition. In this work, the comparative study of PC and ATC was conducted for the reliability of board level interconnects. The comparison was made using both ceramic and organic flip chip ball grid array packages. Moire interferometry was adopted for the experimental stress analysis. In PC simulation, computational fluid dynamics analysis and finite element analysis are performed. The assembly deformations in numerical simulation are compared with those obtained by Moire images. It is confirmed that for a certain organic package PC can be a more severe condition that causes solder interconnects to fail earlier than in ATC while the ceramic package fails earlier in ATC always.