Sorawat Chivapreecha

Bi-Minimax Design of Even-Order Variable Fractional-Delay FIR Digital Filters

This paper proposes a new minimax method for designing even-order finite-impulse-response (FIR) variable fractional-delay (VFD) digital filters with both the peak errors (maximum absolute errors) of variable frequency response (VFR) and VFD response being minimized. We call such a new minimax design the bi-minimax design, which minimizes a mixed error function that contains both the VFR peak error and VFD peak error. A relative weighting factor is used in the mixed error function for adjusting the relative weightings of the two peak errors. The central part of the biminimax design is how to formulate the biminimax design with highly non-linear constraints on the VFD errors as a solvable one. After linearizing the highly non-linear constraints as linear ones, the biminimax design problem can be easily solved by using the well-known efficient software SeDuMi. As a result, both the VFR peak error and VFD peak error can be simultaneously suppressed and the resulting VFR errors and VFD errors are made nearly equiripple (bi-equiripple). As compared with the existing SOCP-based minimax design that minimizes only the VFR peak error, the proposed biminimax method can achieve a nearly biequiripple design for both the VFR and VFD errors. A design example is given to illustrate the effectiveness of the biminimax design method.

An efficient filter structure for multiplierless Sobel edge detection

This paper presents a multiplierless Sobel edge detection filter structure based on the gradient of Gaussian lowpass filter concept. This concept is same as the idea that used for evaluation of Sobel edge detection kernels. The proposed Sobel edge detection filter structure consists of 4 sets of the so-called lowpass-type 2nd order 1-D DPF (Discrete Pascal Filter) and the filter structure does not need any multipliers, only 14 adders are needed for realization. Consequently, the high efficiency multiplierless Sobel edge detector can be achieved.

Generalized Pascal Matrices, Inverses, Computations and Properties Using One-to-One Rational Polynomial s - z Transformations

This paper proposes a one-to-one mapping between the coefficients of continuous-time (s-domain) and discrete-time (z-domain) IIR transfer functions such that the s -domain numerator/denominator coefficients can be uniquely mapped to the z-domain numerator/denominator coefficients. The one-to-one mapping provides a firm basis for proving the inverses of the so-called generalized Pascal matrices from various first-order s- z transformations. We also derive recurrence formulas for recursively determining the inner elements of the generalized Pascal matrices from their boundary ones. Consequently, all the elements of the whole generalized Pascal matrix can be easily generated through utilizing their neighbourhood, which can be exploited for further simplifying the Pascal matrix generations. Finally, we reveal and prove some interesting properties of the generalized Pascal matrices.

Adaptive Equalization Architecture Using Distributed Arithmetic for Partial Response Channels

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (least mean squares) adaptive algorithm. The filter structure is based on distributed arithmetic (DA), which is able to calculate the inner product by shifting, and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (very high-speed integrated circuit hardware description language) and synthesis using FLEX10K Altera FPGA (field programmable gate array) as target technology and uses Leonardo spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter

Bilinear s-z with frequency transformation using Pascal matrix operation

This paper presents an alternative method used for analog domain to digital domain transformation based on bilinear transform. The Pascal matrix is used to transform analog transfer function on s plane to digital transfer function on z plane. Moreover, the frequency transformation from normalized analog low-pass filter prototype to digital low-pass, high-pass, band-pass and band-stop filter is considered incorporate to Pascal matrix operation. This method can be cleared the computation complexity of original bilinear transform, especially to solve the difficulty in case of higher order of digital filter because all of computation use matrix operation. Therefore, it is easy and appropriate to program this method on personal computer or scientific calculator.

New PTS Method with Coded Side Information Technique for PAPR Reduction in OFDM Systems

In this paper, we propose a new PAPR reduction by using a partial transmit sequences (PTS) method with coded side information (SI) technique. These methods are used in an orthogonal frequency division multiplexing (OFDM) system. The OFDM employs orthogonal sub-carriers for data modulation. These sub-carriers unexpectedly present a large peak to average power ratio (PAPR) in some cases. In order to reduce PAPR, the sequence of input data is partitioned into disjoint sub-block of PTS. If number of sub-block increases, high efficiency of PAPR reduction can be obtained. However, a quite large calculation cost must be demanded and thus it is impossible to obtain the optimum PTS. In the proposed method, we introduce a coded side information technique assuming the pseudo-optimum condition into the PTS. The total calculation cost becomes drastically reduced and side information bits for recovering original data in demodulation. In simulation results, the proposed method demonstrated the improvement of PAPR and bit error rate (BER) performance.

Weighted least-squares design of variable recursive digital filters with guaranteed stability

The stability guarantee is the most important issue in designing variable infinite-impulse-response (IIR) digital filters. This paper presents a new variable substitution method for transforming the denominator coefficients of a variable-IIR-filter into another set of variables such that arbitrary values of the new variables can guarantee the stability of the resulting variable-IIR-filter. That is, the design problem subject to stability guarantee (constrained non-linear design problem) is converted into an unconstrained design problem. As a consequence, the resulting variable-IIR-filters are always guaranteed theoretically. A lowpass variable-IIR-filter design example is given to illustrate the effectiveness of the design formulation.

An FPGA-based implementation of variable fractional delay filter

A variable fractional delay (VFD) filter is widely used in applications such as symbol timing recovery, arbitrary sampling rate conversion and echo cancellation. This paper presents an implementation of variable fractional delay filter on FPGA. The implementation utilizes an efficient structure so called Taylor structure. The main advantage of this structure is to reduce number of multiplier and adder when compared with Farrow structure or modified Farrow structure. The result of implementation will be reported as throughput and area utilization.

A New PAPR Reduction Technique for OFDM-WLAN in 802.11a Systems

In this paper, we proposed a new PAPR reduction technique using selective mapping (SLM) cascade with adaptive peak power reduction (APPR) methods. This technique is used in a system based on Orthogonal Frequency Division Multiplexing (OFDM). OFDM has many orthogonally modulated sub-carriers which unexpectedly produce high peak to average power ratio (PAPR). The high PAPR will occasionally reach the amplifier saturation region and therefore result in signal distortion, which causes bit error rate (BER) degradation. The proposed method, a sequence of input data is rearranged by SLM for the reduction of PAPR and then fed into the APPR process in the proposed system. The APPR method controls the peak levels of the modulation signal by an adaptive algorithm. It reduces modulation signals over a predefined range. The parameter for simulation used standard WLAN in IEEE 802.11a system. In simulation results, the proposed method shows the improvement on PAPR, power spectrum density (PSD) and high performance BER compared with conventional APPR.

A CMOS Median Filter Circuit Design

This paper proposes a median filter circuit design, which the operations are in current mode and based on CMOS technology. Its structure consists of three main parts, the first part is current average circuit, second part is current absolute value circuit, and third part is current minimum circuit. The results of this circuit can be shown using the PSpice simulation program to demonstrate the performances of this circuit