Soumendu Sinha

Fabrication and characterisation of Al gate n-metal–oxide–semiconductor field-effect transistor, on-chip fabricated with silicon nitride ion-sensitive field-effect transistor

In the present study, temperature drift analysis of metal–oxide–semiconductor field-effect transistor (MOSFET) is carried out using silicon nitride/SiO2 as dielectric film. An n-channel depletion-mode MOSFET was fabricated with silicon nitride ion-sensitive field-effect transistor (ISFET) on the same wafer. The study presents the fabrication, simulation and characterisation of MOSFET. The gate of the ISFET is stacked with silicon nitride/SiO2 sensing membrane that was deposited using low pressure chemical vapour deposition. Output and transfer characteristics of on-chip fabricated Al gate MOSFET were obtained in order to study the fabricated ISFET behaviour to be used as pH sensor. Silicon nitride is preferred over SiO2 sensing film/dielectric (in case of MOSFET) which has better sensitivity and low drift. Process and device simulations were performed using Silvaco® TCAD tool.

Simulation and characterization of dual-gate SOI MOSFET, on-chip fabricated with ISFET

The paper presents the process design, simulation and characterization of a silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG MOSFET) with Al metal gate. The proposed structure is an N-channel device, using aluminum nitride (AlN) as gate dielectric. The fully depleted SOI-based DG ISFET compatible with the complementary metal-oxide-semiconductor (CMOS) process is considered to be a very promising bio-chemical sensor. Silvaco® TCAD tool is used to perform process design and simulations. The simulated and experimental results are compared, and are found to be in good agreement.

Modeling and simulation of ion-sensitive field-effect transistor using TCAD methodology

Ion Sensitive Field Effect Transistor (ISFET) is a popular potentiometric sensor which can be used for chemical and biochemical sensing. This paper presents the modeling of the electrolyte-insulator-semiconductor structure of ISFET using Silvaco TCAD tool. The electrolyte region along with reference electrode has been modeled as a semiconductor with suitable parameters calculated analytically. Silicon nitride is used as the sensing film and it is observed that a sensitivity of 57.143 mV/pH is obtained for pH sensing application. The effect of using different sensing film thicknesses has also been studied and presented. It is observed that the sensitivity of the device reduces as the sensing film thickness is increased.

Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si 3 N 4 ISFET

This paper reports the fabrication of n-type MOSFET using Si3N4 as dielectric on the same wafer as ISFET for ISFET characterization. The paper presents the fabrication, simulation and characterization of metal-oxide field-effect transistor (MOSFET). The gate of the ISFET is stacked with Si3N4 sensing membrane layer that has been deposited using LPCVD system to cover the gate area. Output and transfer characteristics of on-chip fabricated MOSFET are obtained and measured in order to study the fabricated ISFET behavior to be used as pH sensor. Silicon nitride is preferred over silicon dioxide sensing film/dielectric (in case of MOSFET) which has better sensitivity and low drift. Process simulations were performed using Silvaco® TCAD tool.

Simulation, fabrication and characterization of Dual-Gate MOSFET test structures

Ion-Sensitive Field-Effect Transistor (ISFET) is a popular potentiometric chemical/bio-chemical sensor. However, due to charge screening, the sensitivity of the device is significantly reduced. A logarithmic dependence is exhibited between the charge present at the electrolyte-insulator interface and the charge mirrored in the conducting channel, which limits the sensitivity of an ideal conventional ISFET to 59.2 mV/pH, also known as the Nernstian limit. Using Dual-Gate effect in Silicon-on-Insulator (SOI) technology improves the sensitivity of ISFET. MOSFET test structures are generally fabricated along with ISFETs on the same wafer. In this paper, we have demonstrated the dual gate operation of a Near-Fully Depleted (NFD) SOI MOSFET, by simulating its behavior in SILVACO™ TCAD tool and validating it with the test results of fabricated NFDSOI MOSFET. It is observed that the threshold voltage and drain current of the transistor can be manipulated by applying a potential to the back gate.