Soumitra Pal

Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time (TRA), and write access time (TWA) are also presented. The proposed cell achieves 1.12×/1.43×/5.62× improvement in TRA compared to TG8T/D6T/SE8T at a penalty of 1.1×/4.88× in TWA compared to D6T/TG8T and 1.19×/1.18× in read/write power consumption compared to D6T. An improvement of 1.12×/2.15× in RSNM is observed compared to D6T/TG8T. The proposed cell consumes 5.38× less power during hold mode and also shows 2.33x narrower spread in hold power @ VDD = 0.4 V compared to D6T SRAM cell.

9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue

Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly in deep-subthreshold regime. Furthermore, it does not support column bit-interleaving architecture. Therefore, it is very much prone to multibit soft error. In this paper, a double-ended read-decoupled ultralow-power 9-T SRAM cell (LP9T) is proposed, and the proposed cell supports the column bit-interleaving architecture. Because of read-decoupled technique, its noise tolerance is improved. To show the effectiveness of the proposed cell, it is compared with other recently published SRAM cells, namely, fully differential 8 T (FD8T), single-ended read-disturb-free 9 T (SEDF9T), and ultradynamic voltage scalable 10 T (UDVS10T). The proposed cell provides 1.2×/2.3× higher read current IREAD compared with UDVS10T/SEDF9T. Furthermore, LP9T shows 3.8×/11.6× improvement in read delay compared with FD8T/UDVS10T. The proposed cell achieves 3.9× higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with FD8T. Moreover, LP9T consumes 2.1×/2.1×/4.9× lower hold power HPower during hold mode compared with FD8T/UDVS10T/SEDF9T. The proposed cell also exhibits 1.5×/4.3×/1.25× narrower spread (i.e., more reliable) in IREAD/RSNM/HPower compared with UDVS10T/FD8T/SEDF9T. Furthermore, as the proposed cell supports bit-interleaving architecture, error checking and correction technique can be used to mitigate the issue related to multibit soft error. All these benefits are achieved by the LP9T at a cost of 1.17×/1.17×/1.25× longer write delay compared with FD8T/UDVS10T/SEDF9T.

Comparative study of CMOS- and FinFET-based 10T SRAM cell in subthreshold regime

This article presents a variability resilient FinFET based 10T SRAM cell. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional MOSFET based 10T SRAM cell. The FinFET based SRAM cell offers 2.33× and 1.29× improvements in Read Access Time (T_RA) and Write Access Time (T_WA) respectively. The proposed bitcell also offers 7.06× and 1.54× improvements in T_RA and T_WA variability respectively compared to its MOSFET counterpart. Moreover, our bitcell exhibits 20% higher read static noise margin (RSNM) at a cost of 5% reduction in write static noise margin @ 400 mV.

Implementation of FinFET based STT-MRAM bitcell

DGMOSFET or FinFET has emerged as a promising candidate to replace conventional MOSFET which suffers from various disadvantages like subthreshold leakage, gate-dielectric leakage, SCE (short-channel effect) or DIBL (drain-induced barrier lowering). Emerging technology like FinFET reduces these and improves variability. This paper presents a FinFET based STT-MRAM bitcell which is gaining researchers attention gradually by its nonvolatile nature and low power consumption. It proposes a 2-FinFETs, 1-MTJ based STT-MRAM bitcell to improve its performance metrics. Simulation results in HSPICE show that our proposed bitcell has less probability of read failure, write failure.

Variation-resilient CNFET-based 8T SRAM cell for ultra-low-power application

Local and global process fluctuations causes increase in threshold voltage (V,) variation in ultra-short channel devices like CMOS. Therefore, it is not possible to operate the CMOS based 6-Transistor (6T) SRAM cell bellow 600 mV. Hence, to mitigate the effect of process fluctuations a CNFET based 8T SRAM cell is proposed in this article. Different design metrics of an SRAM cell are accessed for the proposed cell and to show its effectiveness, the design metrics are compared with its conventional counterpart. The proposed cell consumes 2.06× less power during hold mode and it also offers improvement in write delay (read delay) by 5.23× (4.41×) @ 200 mV compared to conventional CMOS based 8T cell. It depicts its robustness against process fluctuations by showing narrower spread in write delay (95.17%), read delay (75.20%) and hold power consumption (87.34%) for the same supply voltage. The proposed CNFET based 8T cell shows 59.41% higher read stability @ 400 mV than the CMOS based 8T SRAM cell.

Device bias technique to improve design metrics of 6T SRAM cell for subthreshold operation

At present day SRAM cell is under renewal stage. Researchers are aiming to get an SRAM cell which is reliable and robust against process, voltage and temperature (PVT) fluctuations. An SRAM cell is also expected to support low-power applications. This article proposes a new way for designing an SRAM cell. The proposed cell functions properly even bellow subthreshold region. Therefore, it can be useful for ultralow-power applications. Robustness/reliability of the proposed design is investigated by estimating read static noise margin (RSNM). The estimated results are compared with its conventional counterpart. The proposed 6T SRAM cell offers 1.83× faster read operation. It is also less affected by PVT fluctuations (by 1.47×) during read operation compared to conventional 6T SRAM cell. The proposed SRAM cell exhibits 1.40× higher RSNM compared to conventional 6T SRAM cell, proving its reliability during read operation. It also shows 3.86% faster write operation. It is 18.4% less affected by PVT fluctuations. It has 2.33% higher write static noise margin (WSNM) than the conventional 6T SRAM cell.

Stability and variability enhancement of 9T SRAM cell for subthreshold operation

This article presents a new way for designing a more reliable and variability resilient 9T SRAM cell which is based on DTMOS (dynamic threshold MOS) and CCBB (cell content body bias) technique under subthreshold operation. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional 9T SRAM cell. The proposed 9T SRAM cell shows 41.8% (9.5%) lower read access time (write access time) compared to conventional 9T SRAM cell. It also exhibits robustness by achieving narrower spread in read access time (write access time) by 53.01% (8%) compared to its conventional 9T SRAM cell. Moreover, the proposed bitcell offers 9.5% (47.4%) improvement in read static noise margin (write static noise margin) @ 350 mV.

A single ended write double ended read decoupled 8-T SRAM cell with improved read stability and writability

In this paper a single ended write double ended read decoupled SRAM cell is proposed. Design metrics of the proposed cell are examined and compared with conventional 6-T. Proposed SRAM cell offer improvement during both read and write operation in terms of speed. It offers 2.95× shorter read delay. It exhibits 2.74× and 7.84× shorter write delay during write-1 and write-0 respectively. The proposed cell also shows improvement in read stability and writability. It offers 5.07× higher RSNM (read static noise margin). It shows 4.08% improvement in WSNM (write static noise margin) @ 300 mV compared to conventional 6-T.

Low-Leakage, Low-Power, High-Stable SRAM Cell Design

This paper proposes a technique for designing low-leakage stable SRAM cell which can mitigate impact of V t (threshold voltage) variation. The architecture of the proposed transmission gate-based 9-transistor SRAM cell (TG9T) is almost similar to that of 7-transistor SRAM cell (7T) except the access transistors, which are replaced with transmission gates. In this study, various key design metrics like noise margin, leakage current, and hold power are simulated for both cells and compared. The proposed design provides 1.25× lower leakage current and 1.46× higher SINM (static current noise margin) while bearing 3.8× penalty in WTI (write trip current) compared with 7T. Proposed design exhibits its robustness by achieving 1.1× tighter spread in hold power compared to 7T.

Design of a Low-Delay-Write Model of a TMCAM

In this paper, a novel version of Ternary Magnetic-Content-Addressable Memory (TMCAM) is proposed for a low-delay-write operation. This is attained from the connections of circuit and majorly due to the exceptional operational features of CAM integrated with MTJ. While the previous TMCAM required each one of the MTJ to be written separately, this model attempts to nullify the problem. Consequently, a reduction in delay by almost twice is obtained in comparison to the previous TMCAM with a 22 nm CMOS technology used for simulation purposes. This can be effectively employed in adaptive biomedical signal processing applications where writing is often and hence, delay cannot be compromised.