Is this you? Create Your Porfile
Avatar

Sreenivasa Chalamala

Advanced Micro Devices

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Explore More

Hotspot

Dive into the research topics where Sreenivasa Chalamala is active.

Explore More

Publication

Featured researches published by Sreenivasa Chalamala.

Archive | 2008

ANALOG COMPARATOR COMPRISING A DIGITAL OFFSET COMPENSATION

Sreenivasa Chalamala; Matthias Baer

Archive | 2008

INTEGRATED CIRCUIT HAVING A MEMORY WITH A PLURALITY OF STORAGE CELLS OF SYNCHRONOUS DESIGN AND CONNECTED TO CLOCK GATING UNITS

Peer Schlegel; Matthias Baer; Sreenivasa Chalamala; Thomas Otto

Archive | 2009

SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUITRY HAVING A PLURALITY OF DEVICES OF REDUCED MISMATCH

Matthias Baer; Sreenivasa Chalamala; Karl-Heinz Sandig

Archive | 2009

Halbleiterbauelement mit analoger Schaltung mit mehreren Bauelementen mit geringerer Fehlanpassung

Matthias Baer; Sreenivasa Chalamala; Karl-Heinz Sandig

Archive | 2008

Analog to digital offset compensation

Matthias Baer; Sreenivasa Chalamala

Archive | 2008

ESD-Leistungsklemmeinrichtung mit stabiler Einschaltfunktion

Sreenivasa Chalamala; Matthias Baer

Archive | 2008

Integrated circuit with a memory having a plurality of memory cells with synchronous structure, which are connected to Taktausblendeeinheiten

Matthias Baer; Sreenivasa Chalamala; Thomas Otto; Peer Schlegel

Archive | 2008

Integrated circuit with a memory having a plurality of memory cells with synchronous structure, which are connected to Taktausblendeeinheiten, and method of designing such a circuit,

Matthias Baer; Sreenivasa Chalamala; Thomas Otto; Peer Schlegel

Archive | 2008

Integrierte Schaltung mit einem Speicher mit mehreren Speicherzellen mit synchronem Aufbau, die mit Taktausblendeeinheiten verbunden sind, sowie Verfahren zum Entwerfen einer solchen Schaltung Integrated circuit with a memory having a plurality of memory cells with synchronous structure, which are connected to Taktausblendeeinheiten, and method of designing such a circuit,

Matthias Baer; Sreenivasa Chalamala; Thomas Otto; Peer Schlegel

Archive | 2008

Integrierte Schaltung mit einem Speicher mit mehreren Speicherzellen mit synchronem Aufbau, die mit Taktausblendeeinheiten verbunden sind Integrated circuit with a memory having a plurality of memory cells with synchronous structure, which are connected to Taktausblendeeinheiten

Matthias Baer; Sreenivasa Chalamala; Thomas Otto; Peer Schlegel

Explore More

Collaboration

Dive into the Sreenivasa Chalamala's collaboration.

Top Co-Authors
Avatar

Matthias Baer

Advanced Micro Devices

View shared research outputs
Top Co-Authors
Avatar

Peer Schlegel

Advanced Micro Devices

View shared research outputs
Top Co-Authors
Avatar

Karl-Heinz Sandig

Advanced Micro Devices

View shared research outputs
Explore More
Researchain Logo
Decentralizing Knowledge