Sriadibhatla Sridevi

Low complexity architecture of linear periodically time varying filter based on a switching representation

This paper presents a low complexity architecture for a linear periodically time varying (LPTV) filter. This architecture is based on input switching representation of LPTV filters. This representation consists of a bank of linear time invariant (LTI) filters with a periodic switch at the input. Due to the switching operation at the input there will be zeros introduced in the input signals of the LTI filters. These zeros will result in futile multiplications. In this paper we develop an efficient architecture by removing these multiplication operations. This architecture is generalization of direct form. The proposed architecture has been synthesized and implemented on Virtex 2pv30-7ff896 FPGA.

A Microwatt Low Voltage Bandgap Reference for Bio-medical Applications

In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area.

Low power and low complexity implementation of LPTV interpolation filter

This paper presents an architecture for low power and low complexity implementation of a linear periodically time varying (LPTV) interpolation filter using thread decomposition (TD) technique which decomposes a filter into finite computational threads. TD technique enables us to develop the proposed architecture as a generalization to linear time invariant (LTI) filter structure. The area complexity of the proposed architecture is significantly reduced by optimizing the concurrent threads of the conventional design. Reduction of power consumption is achieved in the proposed design by eliminating futile multiplications and reducing the operating frequency of the multipliers. It involves nearly one fourth the number of adders, multipliers and delay elements compared to the conventional design. The proposed structure is implemented on Virtex FPGA 2vp30-7ff896. From the synthesis results, it is found that the proposed design offers 35.7% reduction in power consumption and 20.6% reduction in device utilization over the conventional design.