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Network Processor Design#R##N#Issues and Practices Volume 2 | 2004

Implementing Voice over AAL2 on a Network Processor

Jaroslaw J. Sydir; Prashant R. Chandra; Alok Kumar; Sridhar Lakshmanamurthy; Longsong Lin; Muthaiah Venkatachalam

Publisher Summary The flexibility and programmability of next-generation network-processing units (NPU) make them a key component of next-generation telecommunications equipment. NPUs can support a variety of packet-processing applications, with a variety of different requirements. This chapter discusses the special requirements and challenges presented by the Voice over AAL2 (VoAAL2) application. The architecture and design of a VoAAL2 application developed for the Intel IXP2400 processor is described, and the features of an NPU that are required to support this type of application are discussed. With strict quality of service requirements and asynchronous inputs, VoAAL2 can be performed on an NPU. The application is most naturally implemented using an asynchronous programming model. It is found that the IXP2400 naturally supports such a programming model. Support for asynchronous components that span microengines can be improved by adding support for a distributed lock manager.


Archive | 2003

Intel Corporation—Intel IXP2400 Network Processor: A Second-Generation Intel NPU

Prashant R. Chandra; Sridhar Lakshmanamurthy; Raj Yavatkar

Publisher Summary Next generation access and edge equipment requires flexible programming, high performance, low power consumption, and small real estate. In context to this, Intel has developed a next-generation network processor, the IXP2400, which is optimized to meet these requirements. The Intel IXP2400 network processor delivers a new level of intelligence and performance for access and edge applications, enabling the realization of quality of service (QoS), enforcement of service-level agreements (SLAs), and traffic engineering at OC-48/2 .5 Gbps and 4 Gbps data rates. The flexible media interface allows a variety of media devices, ranging from OC3 to OC48 speeds to be connected without logic to the IXP2400 for easier design and lower system cost. These capabilities essentially allow OEMs and service providers to offer differentiated and tiered services to their customers while efficiently managing their network resources and bandwidth. The performance and flexibility of the IXP2400 makes it desirable for a wide variety of high-performance applications such as multiservice switches, DSLAMs (DSL access multiplexers), CMTS (cable modem termination system) equipment, 2.5G and 3G wireless infrastructure, and layer 4-7 switches.


IEEE Micro | 2015

Intel Atom C2000 Processor Family: Power-Efficient Datacenter Processing

Bradley Burres; Johan van de Groenendaal; Praveen Mosur; Jonathan Robinson; Ian M. Steiner; Yi-Feng Liu; Sin S. Tan; Erik A. McShane; Belliappa Kuttanna; Sridhar Lakshmanamurthy

The Intel Atom C2000 Microserver, codenamed Avoton and Rangeley, is a complete server and embedded processor system on chip (SoC) that provides up to seven times greater performance and six times the energy efficiency versus the prior-generation processor. Leveraging the Atom Silvermont microarchitecture, Intels 22-nm tri-gate manufacturing process and a robust set of integrated I/O, Intel is expanding its reach into datacenter computing.


Archive | 2003

Intel Corporation—Intel IXP2400 Network Processor

Prashant R. Chandra; Sridhar Lakshmanamurthy; Raj Yavatkar

Publisher Summary Next generation access and edge equipment requires flexible programming, high performance, low power consumption, and small real estate. In context to this, Intel has developed a next-generation network processor, the IXP2400, which is optimized to meet these requirements. The Intel IXP2400 network processor delivers a new level of intelligence and performance for access and edge applications, enabling the realization of quality of service (QoS), enforcement of service-level agreements (SLAs), and traffic engineering at OC-48/2 .5 Gbps and 4 Gbps data rates. The flexible media interface allows a variety of media devices, ranging from OC3 to OC48 speeds to be connected without logic to the IXP2400 for easier design and lower system cost. These capabilities essentially allow OEMs and service providers to offer differentiated and tiered services to their customers while efficiently managing their network resources and bandwidth. The performance and flexibility of the IXP2400 makes it desirable for a wide variety of high-performance applications such as multiservice switches, DSLAMs (DSL access multiplexers), CMTS (cable modem termination system) equipment, 2.5G and 3G wireless infrastructure, and layer 4-7 switches.


Network Processor Design | 2003

Chapter 13 – Intel Corporation—Intel IXP2400 Network Processor: A Second-Generation Intel NPU

Prashant R. Chandra; Sridhar Lakshmanamurthy; Raj Yavatkar

Publisher Summary Next generation access and edge equipment requires flexible programming, high performance, low power consumption, and small real estate. In context to this, Intel has developed a next-generation network processor, the IXP2400, which is optimized to meet these requirements. The Intel IXP2400 network processor delivers a new level of intelligence and performance for access and edge applications, enabling the realization of quality of service (QoS), enforcement of service-level agreements (SLAs), and traffic engineering at OC-48/2 .5 Gbps and 4 Gbps data rates. The flexible media interface allows a variety of media devices, ranging from OC3 to OC48 speeds to be connected without logic to the IXP2400 for easier design and lower system cost. These capabilities essentially allow OEMs and service providers to offer differentiated and tiered services to their customers while efficiently managing their network resources and bandwidth. The performance and flexibility of the IXP2400 makes it desirable for a wide variety of high-performance applications such as multiservice switches, DSLAMs (DSL access multiplexers), CMTS (cable modem termination system) equipment, 2.5G and 3G wireless infrastructure, and layer 4-7 switches.


Archive | 2005

Instruction-assisted cache management for efficient use of cache and memory

Mark B. Rosenbluth; Sridhar Lakshmanamurthy


Archive | 2002

Method and apparatus to assemble data segments into full packets for efficient packet-based classification

Sridhar Lakshmanamurthy; Charles Narad; Lawrence B. Huston; Yim Pun; Raymond Ng; Debra Bernstein; Mark B. Rosenbluth


Archive | 2002

Method and apparatus to communicate flow control information in a duplex network processor system

Sridhar Lakshmanamurthy; Lawrence B. Huston; Yim Pun; Raymond Ng; Hugh Wilkinson; Mark B. Rosenbluth; David Romano


Archive | 2005

Memory controller with bank sorting and scheduling

Sridhar Lakshmanamurthy; Dharmin Y. Parikh; Karthik Vaithianathan; Gary Lavelle; Atul Kwatra


Archive | 2005

Two stage queue arbitration

Sridhar Lakshmanamurthy; Hugh Wilkinson

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