Srijib Narayan Maiti
STMicroelectronics
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Publication
Featured researches published by Srijib Narayan Maiti.
3dtv-conference: the true vision - capture, transmission and display of 3d video | 2012
Srijib Narayan Maiti; Parth Desai; Bhargav Patel; Yuvraj Goel; Emiliano Piccinelli; Davide Aliprandi; Pasqualina Fragneto; Beatrice Rossi
In this paper we explore a method to encode/decode multiview textures and associated supplementary data (depth map as an example) together in a single bitstream. Least significant bit (LSB) of last two levels in each transform block has been modified according to the depth encoded bits, thus resulting in very minimal loss in PSNR of textures (0.1 - 0.5dB) with overall bitrate gain of about 13% for natural scenes. The remaining encoded information have been inserted after the slice NAL of corresponding texture ensuring backward compatibility and correct extraction and decoding by a modified decoder. Benchmarking results in terms of compression efficiency and quality on HD sequences have been reported to explore further the viability of using this technique for Free Viewpoint Video (FVV) or 3DV use cases. Experiments are also carried out to evaluate subjective quality of the synthesized views.
picture coding symposium | 2012
Srijib Narayan Maiti; Parth Desai; Bhargav Patel; Emiliano Piccinelli; Davide Aliprandi; Pasqualina Fragneto; Beatrice Rossi
In this paper we propose a method to encode/decode multiview textures and associated depth maps together in a single bitstream. Encoded bits of depth maps have been merged into that of associated textures in an innovative way with very minimal loss in PSNR of textures, 0.1-0.2 dB for high delay and 0.2-1 dB for low delay applications. Benchmarking results in terms of compression efficiency and quality on HD sequences have been reported to explore the viability of using this technique for Free-view point Video (FVV) or 3DV use cases.
electronic imaging | 2006
Abhik Sarkar; Kaushik Saha; Srijib Narayan Maiti
The demand for real-time MPEG decoding is growing in multimedia applications. This paper discusses a hardware-software co-design for MPEG-2 Video decoding and describes an efficient parallel implementation of the software module. We have advocated the usage of hardware for VLD since it is inherently serial and efficient hardware implementations are available. The software module is a macro-block level parallel implementation of the IDCT and Motion Compensation. The parallel implementation has been achieved by dividing the picture, into two halves for 2-processor implementation and into four quadrants for 4-processor implementation, and assigning the macro-blocks present in each partition to a processor. The processors perform IDCT and Motion Compensation in parallel for the macro-blocks present in their allotted sections. Thus each processor displays 1/no_of_processors of a picture frame. This implementation minimizes the data dependency among processors while performing the Motion Compensation since data dependencies occur only at the edges of the divided sections. Load balancing among the processors has also been achieved, as all the processors perform computation on an equal number of macro-blocks. Apart from these, the major advantage is that the time taken to perform the IDCT and Motion Compensation reduces linearly with an increase in number of processors.
Archive | 2009
Amit Gupta; Srijib Narayan Maiti
Archive | 2005
Kaushik Saha; Abhik Sarkar; Srijib Narayan Maiti
Archive | 2004
Kaushik Saha; Srijib Narayan Maiti; Marco Cornero
Archive | 2003
Kaushik Saha; Srijib Narayan Maiti
Archive | 2003
Kaushik Saha; Srijib Narayan Maiti
Archive | 2012
Emiliano Piccinelli; Pasqualina Fragneto; Davide Aliprandi; Beatrice Rossi; Srijib Narayan Maiti
international conference on signal processing and multimedia applications | 2009
Srijib Narayan Maiti; Amit Gupta; Emiliano Piccinelli; Kaushik Saha