Stamatios V. Kartalopoulos

An associative RAM-based CAM and its application to broadband communications systems

The content addressable memory (CAM) is a memory device that executes fast recognition and validation of binary patterns of a limited set, as opposed to the random access memory (RAM) that executes slow recognition of a large set of patterns. Here, we present a logic circuit which, combined with existing RAMs, constructs an associative RAM-based content addressable memory (AR-CAM) that executes fast pattern recognition of very large pattern sets. In addition, we describe the applicability of the AR-CAM to broad-band communications systems. Broadband communications systems with an aggregate bandwidth of tens or hundreds of Gbps require real-time recognition and translation of large pattern sets. Although CAMs are a good candidate for such applications, nevertheless we demonstrate that AR-CAMs can better and inexpensively accomplish this task.

Disaster avoidance in the Manhattan Fiber Distributed Data Interface Network

The Manhattan Fiber Distributed Data Interface (MFDDI) Network, also known as token-grid network, is a two-connected high-speed network, that exhibits the routability properties of a mesh network and the practicality of high-speed dual ring networks such as the FDDI. The MFDDI network is comprised of a set of networks, similar but not limited to FDDI, whereby the member networks are interconnected so that nodes form a grid. In addition, the MFDDI network transmits packetized information and is characterized by built-in flexibility, specific comprehensive protocols, fault-tolerant properties, and superior throughput performance. The MFDDI network has the ability to select the best available route from a number of possible ones, between source and destination nodes. Herein, the networks ability to survive with faulty nodes and/or in disaster situations is described and illustrated. Due to its self synchronization properties, the MFDDI provides a potential solution to network survivability of the upcoming ATM networks.<<ETX>>

A Manhattan fiber distributed data interface architecture

The Manhattan street network (MSN) is a two-connected regular mesh network, applicable to local area networks, that exhibits an increased throughput performance. The fiber distributed data interface (FDDI) single-loop token ring local area network exhibits high data rate over fiber medium and self-restoring properties. A two-connected regular mesh network topology with FDDI, called M-FDDI, with a node capacity in excess of 250000 is presented. The M-FDDI network exhibits high data rate (100 Mbps or higher) and self-restoration. Control in the M-FDDI is fully distributed, and each node is capable of knowing the status of the other nodes to determine the best route and avoid deadlock conditions. The network is expandable by incorporating standard network expansion practices allowing for other LANs or long haul networks to be connected.<<ETX>>

Classification of Exclusive-Or structures in the minimization of logic functions

A class of irreducible logic functions is classified. Mapping of these functions results in symmetric and/or antisymmetric structures which are reducible with Exclusive-Or operations only. Ortho-, reverse-, symmetric and antisymmetric structures are defined. These principles arc used in identifying such structures in logic functions and thus are further reduced. Examples illustrate their use in the minimization of more general logic functions.

Signal processing and implementation of motion detection neurons in optical pathways

The signal processing and the communication paths of the visual neural network are reviewed. The organization and communication of neurons in the visual system and artificial directional retina neurons are described. An electronic circuit behaving like the directional neurons of the retina provides directional information about and the speed of motion of a moving object. The obtained information is then processed by higher-level artificial neurons in the optical pathway.<<ETX>>

Associative RAM-based CAM applicable to packet-based broadband systems

Content addressable memories (CAM) are devices for fast pattern recognition of a limited set, as opposed to random access memories (RAM) that execute slow pattern recognition of a large set of patterns. Associative RAM-based content addressable memories (AR-CAM) combine fast pattern recognition and very large pattern sets. In this paper, we describe the applicability of AR-CAMs to ultra-high speed packet-based broadband communications systems with aggregate bandwidths of hundreds of Gbps, such as ATM and Internet.

A global multi-satellite network for multi-media and PCS services with fault and disaster avoidance characteristics

Multi-satellite communication networks have been proposed to address the explosive growth in global multi-media and personal communications services. A satellite network, must provide continuous, error-free, and uninterrupted high-throughput transmission even if one or more satellites in the network fail. Consequently, fault tolerance, disaster avoidance and network survivability of a satellite network are important characteristics. Herein, a fully connected global multi-satellite network is presented and its fault tolerance, disaster avoidance, network survivability, and traffic capacity of the network are discussed.

Linear dynamic feedback sequential machines with matrix memory implementation

The analysis and design of linear dynamic feedback sequential machines implemented with matrix memories, such as read only memories, is presented. Such machines differ from direct feedback sequential machines with no external inputs in that they may enter or exit any trap state or loop at any specified time; each particular machine is defined by an external control input. This control input may come from the external world or the output of another memory or a processing computer. Consequently, these machines may be considered as adaptive machines. Additionally, they are programmable, the same machine may be designed to satisfy requirements of a variety of applications in discrete-time control systems.

The minimization of logic functions utilizing two-dimensional representations of hypercubes

A novel graphical method for the minimization of logic functions of many variables in presented. It is based on a two-dimensional representation of the hypercube which specifies the multi-variate logic function. A two-dimensional graph of vectors is obtained in which each vector represents an edge of the hypercube. Procedures and rules are developed to minimize logic functions on such a graph. This method in simple, fast, and overcomes some of the significant disadvantages of previous tabular techniques.