Stanislas Baron

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

The use of customized illumination modes is part of the pursuit to stretch the applicability of immersion ArF lithography. Indeed, a specific illumination source shape that is optimized for a particular design leads to enhanced imaging results. Recently, freeform illumination has become available through pixelated DOEs or through FlexRayTM, ASMLs programmable illuminator system, allowing for virtually unconstrained intensity distribution within the source pupil. In this paper, the benefit of freeform over traditional illumination is evaluated, by applying source mask co-optimization (SMO) for an aggressive use case, and wafer-based verification. For a 22 nm node SRAM of 0.099 μm² and 0.078 μm2 bit cell area, the patterning of the full contact and metal layer into a hard mask is demonstrated with the application of SMO and freeform illumination. In this work, both pixelated DOEs and FlexRay are applied. Additionally, the match between the latter two is confirmed on wafer, in terms of CD and process window.

Source mask optimization methodology (SMO) and application to real full chip optical proximity correction

Due to the continuous shrinking in half pitch and critical dimension (CD) in wafer processing, maintaining a reasonable process window such as depth of focus (DOF) & exposure latitude (EL) becomes very challenging. With the source mask optimization (SMO) methodology, the lithography process window can be improved and a smaller mask error enhancement factor (MEEF) can be achieved. In this paper, the Tachyon SMO work flow and methodology was evaluated. The optimum source was achieved through evaluation of the critical designs with Tachyon SMO software and the simulated performance was then verified on another test case. Criteria such as DOF, EL & MEEF were used to determine the optimum source achieved from the evaluation. Furthermore, the process variation band (PV-Band) and the number of hot spot (design weak points) were compared between the POR and the optimum source. The simulation result shows the DOF, MEEF & worst PV-Band were improved by 13%, 17% & 12%, respectively with the optimum SMO source. In order to verify the improvement from the optimum SMO at the silicon level, a new OPC model was recalibrated with wafer CD from the optimized source. The OPC recipe was also optimized and a reticle was retrofitted with the new OPC. By comparing the process window, hotspots and defects between the original vs. new reticle, the benefit of the optimized source was verified on silicon.

Model based OPC for implant layer patterning considering wafer topography proximity (W3D) effects

Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage of non-uniform reflective substrates without bottom anti-reflection coating (BARC). Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without BARC, e.g., implant layer, as technology node shrinks. For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full chip OPC on implant layers.

Process window enhancement using advanced RET techniques for 20nm contact layer

At the 20nm technology node, it is challenging for simple resolution enhancements techniques (RET) to achieve sufficient process margin due to significant coupling effects for dense features. Advanced computational lithography techniques including Source Mask Optimization (SMO), thick mask modeling (M3D), Model Based Sub Resolution Assist Features (MB-SRAF) and Process Window Solver (PW Solver) methods are now required in the mask correction processes to achieve optimal lithographic goals. An OPC solution must not only converge to a nominal condition with high fidelity, but also provide this fidelity over an acceptable process window condition. The solution must also be sufficiently robust to account for potential scanner or OPC model tuning. In many cases, it is observed that with even a small change in OPC parameters, the mask correction could have a big change, therefore making OPC optimization quite challenging. On top of this, different patterns may have significantly different optimum source maps and different optimum OPC solution paths. Consequently, the need for finding a globally optimal OPC solution becomes important. In this work, we introduce a holistic solution including source and mask optimization (SMO), MB-SRAF, conventional OPC and Co-Optimization OPC, in which each technique plays a unique role in process window enhancement: SMO optimizes the source to find the best source solution for all critical patterns; Co-Optimization provides the optimized location and size of scattering bars and guides the optimized OPC solution; MB-SRAF and MB-OPC then utilizes all information from advanced solvers and performs a globally optimized production solution.

Cost effective application of advanced computational lithography techniques using flexible mask optimization

The 2x nm technology node, with its very low k1 values using immersion lithography is made possible by using advanced computational lithography. Computational techniques such as accounting for 3D effects (including mask topography, wafer sub-layers and resist profiles) in OPC models, the use of model based assist feature placements and the application of process window based OPC solvers have become essential for addressing critical patterning issues. Although these methods can be complex and computationally expensive there is a cost effective application using a framework known as flexible mask optimization or FMO [1,2]. In this study, we show a successful demonstration of such an approach for an advanced technology node using FMO. In the typical OPC development period, various issues may be found which require additional fine tuning. However, each adjustment of the OPC recipe can have unintended consequences in other parts of the chip. This iterative nature of tuning to correct one design area, only to have to then correct a new design area as a consequence, can be endless and very costly. With this FMO flow, critical patterns were identified, classified and corrected using advanced techniques only in localized areas. FMO uses a model based method to ensure defect free boundaries and guarantees that no hotspots are generated as a result of using multiple correction methods on the same layout. The key advantage for FMO is enabling the application of advanced OPC techniques only where necessary. This study demonstrates flows using various case studies on different types of defects and correction methods. The data shows that by using the FMO approach the critical patterns were corrected with defect free boundaries. Mask rule checks (MRC) for main patterns and SRAF are shown clean for all cases. The cost benef

Manufacturing challenges for curvilinear masks

To achieve the ultimate resolution and process control from an optical (193i 1.35NA) scanner system, it is desirable to be able to exploit both source and mask degrees of freedom to create the imaging conditions for any given set of patterns that comprise a photomask. For the source it has been possible to create an illumination system that allows for almost no restrictions in the location and intensity of source points in the illumination plane [1]. For the mask, it has been harder to approach the ideal continuous phase and transmission mask that theoretically would have the best imaging performance. Mask blanks and processing requirements have limited us to binary (1 and 0 amplitude, or 1 and -0.25 amplitude (6% attenuated PSM)) or Alternating PSM (1, 0 and -1 amplitude) solutions. Furthermore, mask writing (and OPC algorithms) have limited us to Manhattan layouts for full chip logic solutions. Recent developments in the areas of mask design and newly developed Multi-Beam Mask Writers (MBMW) have removed the mask limitation to Manhattan geometries [2]. In this paper we consider some of the manufacturing challenges for these curvilinear masks.

3D resist profile full chip verification and hot spot disposition

For 28 nm technology node and below resist profiles need to be taken in to consideration during optical proximity correction (OPC) and verification. The low k1 results in a shallower depth of focus and thus thinner resists, which combined with the process limits increases the risk of resist degradation. Only considering the resist critical dimensions at a single focal plane (such as at the bottom of the resist stack) will miss the impact of the resist 3D profile, like top loss or bottom footing, which can transfer to etch hard pattern failures. To date, modeling to study resist 3D profiles has been available using rigorous simulators and has been used as a verification method for hot spots captured during full chip OPC verification, but not for full chip verification due to the high computational run time cost. This paper demonstrates a 3D resist compact OPC model concept and implementation in a full chip OPC and verification flow. The results show significant improvement for full chip OPC quality with a good correlation between simulation and real wafer hot spots. Because resist profiles are not directly correlated to etch failure, the relationship between the resist profile and etch failures and how to characterize the threshold to dispose the hot spots for the 3D compact model was also investigated.

Efficient full-chip SRAF placement using machine learning for best accuracy and improved consistency

Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time. Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO). Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy. ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges. In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.

The new OPC method for obtaining the stability of MBAF OPC

Current patterning technology for manufacturing memory devices is being developed towards enabling high density and high resolution capability. However, as applying high resolution technology results in decreased process margin, OPC has to compensate for such effect. Since the process margin is decreased greatly for contact layers, technologies such as RBAF (Rule-Based Assist Feature), MBAF (Model-Based Assist Feature), and ILT (Inverse Lithography Technology) are considered to maximize the process margin [1, 2, 3]. Although ILT is the best solution in terms of process margin, it has several disadvantages such as long OPC run-time, mask complexity, and unstable mask fidelity. MBAF method is a good compromise for more advanced techniques mitigating those risks (but not eliminating it), which is why it is often used for contact layers. When setting up the rules for RBAF, not all patterns are considered. Thus, applying RBAF for contact layers may result in decreased process margin for certain patterns since the same rule is applied globally. MBAF, on the other hand, can maximize the process margin for various patterns as it generates AF (Assist Feature) to locations that maximize the margin for the patterns considered. However, MBAF method is very sensitive to even a slight change of a target, which influences the locations of the AF. This leads to generating different OPCed CD of the main features, even for those that should not be affected by the changed target. Once the OPCed CD is changed, it is impossible to obtain the same mask CD even when the mask is manufactured with the same method. If this case occurs during mass production, the entire layer needs to be confirmed after each revision which leads to unnecessary time loss. In this paper, we suggest a new OPC method to prevent this issue. With this flow, OPCed shapes of unchanged patterns remain the same while only the changed targets are OPCed and replaced into the corresponding location, while the boundaries between those regions are corrected using a model based boundary healing. This method can reduce the overall OPCTAT as well as the time spent in verifying the entire layout after each revision. Details of these results will be described in this paper. After further studies, this flow can also be applied to ILT.

Machine learning assisted SRAF placement for full chip

Sub-Resolution Assist Features (SRAF) are widely used for Process Window (PW) enhancement in computational lithography. Rule-Based SRAF (RB-SRAF) methods work well with simple designs and regular repeated patterns, but require a long development cycle involving Litho, OPC, and design-technology co-optimization (DTCO) engineers. Furthermore, RB-SRAF is heuristics-based and there is no guarantee that SRAF placement is optimal for complex patterns. In contrast, the Model-Based SRAF (MB-SRAF) technique to construct SRAFs using the guidance map is sufficient to provide the required process window for the 32nm node and below. It provides an improved lithography margin for full chip and removes the challenge of developing manually complex rules to assist 2D structures. The machine learning assisted SRAF placement technique developed on the ASML Brion Tachyon platform allows us to push the limits of MB-SRAF even further. A Deep Convolutional Neural Network (DCNN) is trained using a Continuous Transmission Mask (CTM) that is fully optimized by the Tachyon inverse lithography engine. The neural network generated SRAF guidance map is then used to assist full-chip SRAF placement. This is different from the current full-chip MB-SRAF approach which utilizes a guidance map of mask sensitivity to improve the contrast of optical image at the edge of lithography target patterns. We expect that machine learning assisted SRAF placement can achieve a superior process window compared to the MB-SRAF method, with a full-chip affordable runtime significantly faster than inverse lithography. We will describe the current status of machine learning assisted SRAF technique and demonstrate its application on the full chip mask synthesis and how it can extend the computational lithography roadmap.