Stanislav Racek

Segmentation of standard ethernet messages in the time-triggered ethernet

TT Ethernet is a communication architecture which allows the integration of the standard Ethernet traffic and real-time Ethernet traffic in the same network without invalidating the real-time properties of the real-time traffic. The TT Ethernet switch distinguishes between two classes of traffic. The standard Ethernet traffic is handled in conformance with the existing (standard) Ethernet, whereas the real-time traffic is transmitted with a constant transmission delay. In order to guarantee a constant message transmission delay, the TT Ethernet switch preempts, if necessary, the transmission of standard Ethernet messages, and retransmit the preempted Ethernet message as soon as the transmission of the real-time Ethernet message is finished. The message can be preempted several times before it is successfully transmitted, which decreases the throughput of standard Ethernet messages. In this paper, we propose a segmentation mechanism for standard Ethernet frames in order to increase the throughput. The segmentation mechanism does not change the format of Ethernet frame and is transparent to higher levels of a protocol stack such as TCP/IP.

Evaluation of process controller fault tolerance using simulation

Abstract The paper presents a study of several alternatives of a fault-tolerant process controller design. We compare controller architectures based on different amount of hardware redundancy with those using time redundancy. The system behaviour is evaluated by means of a process-oriented simulation model enabling software injection of faults. As an overall measure of controller design quality (which includes both performance and reliability) we use the numerical error of the output. The results obtained on the model are used to show the dependence of the output error upon the relative speed of computation and upon the rate of faults damaging the data. Thus for every set of parameters, a system configuration which gives the best results, can be determined.

Model-Based Dependability Evaluation Method for TTP/C Based Systems

This paper presents a simulation model of the Time-Triggered Protocol (TTP/C) based embedded computer system as a tool for evaluation of system capability to tolerate a chosen category of faults. The model, being written in ANSI-C, is portable and machineindependent. Its structure is modular and flexible, so that the system to be studied and the experiment setting can easily be changed. The functionality of this model is demonstrated on a set of fault injection experiments aimed mainly to evaluate the correctness of the TTP/C specification. These experiments were done within the EU/IST FIT (Fault Injection for Time triggered architecture) project solution.

Reliability of Task Execution During Safe Software Processing

This paper presents the reliability evaluation of task execution during safe software processing. The standard method of duplication in a safety-critical application can also be applied for tasks in a software system. But in addition to this, there is also the possibility for coded task processing to increase the reliability and availability of software. The presented analysis covers the reliability analysis of a single, a duplicated and a coded task by the technique of continuous time Markov processes. Markov processes are often used for the reliability evaluation of safety-critical systems. We introduce a method to describe the execution time of tasks by means of enhanced Markov models and their solution by numerical methods.

C-Sim - the C language enhancement for discrete-time simulation

The paper presents the C-Sim simulation environment, which enables the execution of several processes in an interleaved mode using the global simulation lime concept. C-Sim was used within the EU/IST project Fault Injection for Time Triggered Architecture (FIT) to build a simulation model of TTP/C protocol based real-time embedded computer system in order to verify its dependability through fault injection.

Functional validation of fault-tolerant asynchronous algorithms

The paper presents an alternative approach to the formal specification and validation of distributed asynchronous algorithms. It begins with a syntactically correct description of the algorithm whose correctness is then to be validated. The validation of the algorithm is based on the process-oriented discrete simulation and permits a partial correctness validation of the algorithm implemented by a program. The suggested method enables to model independent activity of several processors (using pseudo-parallel processes) in simulation time and to model communication channels with defined time behavior and failure semantics. Using the approach it is easy to add other processes like model of systems environment, fault injector and state observer. The method is described with the aid of a simple C-based validation tool called C-Sim. The utilization of C-Sim requires only slight changes in C-coded implementation of the verified algorithm. An example of validation of distributed election algorithm with the presence of faults is presented.

Performance Comparison of Distributed Simulation Using PVM and MPI

The main purpose of this paper is to present the possibilities of the simulation programs speedup using parallel processing and to compare results from an example experiments. The solution uses well-known software tools: Parallel Virtual Machine (PVM) and Message Passing Interface (MPI). The comparison of these systems is presented and possibilities of distributed simulation program modular implementation are discussed as well.

Comparison of Enhanced Markov Models and Discrete Event Simulation: For Evaluation of Probabilistic Faults in Safety-Critical Real-Time Task Sets

In this paper we present simulation and model based approaches for evaluating and validating the temporal and safety relevant properties of software intensive safety-critical real-time embedded systems. A high level reliability model of a safe task execution is described by a continuous-time Markov process, enhanced by the modeling of execution times. It is shown that the behavior - regarding real-time and safety metrics - of this theoretical model can be transferred into an abstract system timing model, which then can be analyzed by a discrete event simulation approach. The verification of the discrete event simulation by Markov models offers the possibility of a holistic approach for reliability analysis combined with schedulability analysis of complex safety-critical multicore real-time systems by the discrete event simulation.

Data Flow Analysis of Software Executed by Unreliable Hardware

The data flow is a crucial part of software execution in recent applications. It depends on the concrete implementation of the realized algorithm and it influences the correctness of a result in case of hardware faults during the calculation. In logical circuits, like arithmetic operations in a processor system, arbitrary faults become a more tremendous aspect in future. With modern manufacturing processes, the probability of such faults will increase and the result of a softwares data flow will be more vulnerable. This paper shows a principle evaluation method for the reliability of a softwares data flow with arbitrary soft errors also with the concept of fault compensation. This evaluation is discussed by means of a simple example based on an addition.

Optimizing software integration in component-based embedded systems by using simulated annealing

The definition of the integration order in a component based embedded system is often a crucial part in the software development process. The integration sequence is affected by many parameters and there is a lack of methods to determine an order which fits best. This decision often depends on integrators expertise. This article considers two key parameters of software integration which are present in most development processes and describes an approach to determine a most suitable integration order.