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Dive into the research topics where Stanislaw Deniziak is active.

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Featured researches published by Stanislaw Deniziak.


ieee acm international conference utility and cloud computing | 2014

Cost Optimization of Real-Time Cloud Applications Using Developmental Genetic Programming

Stanislaw Deniziak; Leszek Ciopiński; Grzegorz Pawiński; Karol Wieczorek; Slawomir Bak

This paper presents the methodology for the cost optimization of real-time applications, that are conformable to the Infrastructure as a Service (IaaS) model of cloud computing. We assume, that functions of applications are specified as a set of distributed echo algorithms with soft real-time constraints. Then our methodology schedules all tasks on available cloud infrastructure, minimizing the total costs of the IaaS services, while guaranteeing the required level of the quality of services, as far as real-time requirements are concerned. It takes into account limited bandwidth of communication channels as well as the limited computation power of server nodes. The cost is optimized using the method based on the developmental genetic programming. The method reduces the cost of hiring the cloud infrastructure by sharing cloud resources between applications. We also present experimental results, that show the benefits of using our methodology.


federated conference on computer science and information systems | 2014

An application of developmental genetic programming for automatic creation of supervisors of multi-task real-time object-oriented systems

Krzysztof Sapiecha; Leszek Ciopiński; Stanislaw Deniziak

A concept of artificial supervisor of multi-task real-time object-oriented system is introduced. Next, a procedure for automatic creation of artificial supervisors is presented. The procedure is based on developmental genetic programming. As an input data, UML diagrams are used. A representative example of creation of a supervisor of building a house illustrates the procedure. The efficiency of the procedure from various points of view and comparison considerations are given.


design and diagnostics of electronic circuits and systems | 2009

Contention-avoiding custom topology generation for network-on-chip

Stanislaw Deniziak; Robert Tomaszewski

In this paper we present a methodology for custom topology generation, offering low latency and significantly reduced power consumption. The novelty of our approach lies in the objective - we focus on complete elimination of the contention on the links. It is achieved through alternate path generation, insertion of additional links and message scheduling. We also present a novel concept of Message Dependence Graph for traffic analysis. The methodology operates under application and design constraints, producing network topology along with routing paths. Experimental results confirming benefits of the proposed approach are provided.


engineering of computer-based systems | 2004

Validation of reactive embedded systems against temporal requirements

Joanna Strug; Stanislaw Deniziak; Krzysztof Sapiecha

Efficient methods of automatic generation of test scenarios to validate a system against functional requirements have already been developed. However, there are no such satisfactory methods as far as temporal requirements are concerned. A method of automatic generation of test scenarios for verification of time constraints for reactive embedded systems is presented.


international conference: beyond databases, architectures and structures | 2015

Preserving Data Consistency in Scalable Distributed Two Layer Data Structures

Adam Krechowicz; Stanislaw Deniziak; Grzegorz Łukawski; Mariusz Bedla

The scalable NoSQL systems are often the best solutions to store huge amount of data. Despite that they in vast majority do not provide some features known from database systems (like transactions) they are suitable for many applications. However, in systems that require data consistency, e.g. payments or Internet booking, the lack of transactions is still noticeable. Recently the need of transactions in such data store systems can be observed more and more often. The Scalable Distributed Two Layer Data Structures (SD2DS) are very efficient implementation of NoSQL system. This paper exposes its basic inconsistency problems. We propose simple mechanisms which will be used to introduce consistency in SD2DS.


design and diagnostics of electronic circuits and systems | 2009

A symbolic RTL synthesis for LUT-based FPGAs

Stanislaw Deniziak; Mariusz Wisniewski

In this paper a methodology of symbolic RTL synthesis, for circuits implemented in FPGA devices, is presented. First, symbolic functions are separated from binary and arithmetic ones. Next, the multi-valued logic network is optimized using our methods of symbolic functional decomposition, designed for functions with multi-valued inputs and multi-valued outputs. Finally, the whole circuit is implemented in FPGA device using commercially available tools. The goal of the presented methodology is to minimize the total FPGA area. Presented example showed that our methodology gives better results than existing RTL synthesis tools.


international conference on electronics circuits and systems | 2004

Fast high-level fault simulator

Stanislaw Deniziak; Krzysztof Sapiecha

A new fast fault simulation technique is presented for calculating fault propagation through high level primitives (HLPs). Reduced ordered ternary decision diagrams are used to describe HLPs. The technique is implemented in an HTDD fault simulator. The simulator is evaluated with some ITC99 benchmarks. Besides high efficiency (in comparison with existing fault simulators), it shows flexibility for the adoption of a wide range of fault models.


digital systems design | 2003

An iterative improvement co-synthesis algorithm for optimization of SOPC architecture with dynamically reconfigurable FPGAs

Radosław Czarnecki; Stanislaw Deniziak; Krzysztof Sapiecha

In this work, a HW/SW iterative improvement co-synthesis algorithm, which allows for optimization of heterogeneous system architecture with dynamically reconfigurable FPGAs is presented. The algorithm maximizes speed of the system taking into consideration cost constraints.


IEEE Computer | 2001

Developing a high-level fault simulation standard

Stanislaw Deniziak; Krzysztof Sapiecha

Recent developments in deep-submicron technology challenge current integrated circuit testing methods. The increasing complexity of designed systems makes test development more time-consuming. Moreover, nanometer technology introduces new defects or higher data rate errors. To reduce manufacturing costs and time to market, we must develop efficient fault detection and location methods. Using high-level fault simulation stimulates the development of new, fast test-generation algorithms that take into consideration functional features of the system under test or its components. Moreover, all synthesis tools migrate to higher levels, and we believe that this will improve ATPG tools as well.


international conference: beyond databases, architectures and structures | 2015

Query by Shape for Image Retrieval from Multimedia Databases

Stanislaw Deniziak; Tomasz Michno

Efficient methods of image retrieval is one of the most important challenges in the scope of the management of large multimedia databases. Existing methods for querying, based on a textual description e.g. keywords or based on image content, are not sufficient for the most applications. Methods based on semantic features are more suitable. In this paper we propose a new query by shape (QS) method for image retrieval from multimedia databases. Each image in the database is represented as a set of graphical objects, which are specified using graphical primitives like lines, circles, polygons etc. To retrieve images containing the given object, the object shape should be provided. Next, the efficient algorithm for testing the similarity of shapes is applied. The preliminary results showed the high effectiveness of the QS method.

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Krzysztof Sapiecha

Kielce University of Technology

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Tomasz Michno

Kielce University of Technology

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Adam Krechowicz

Kielce University of Technology

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Leszek Ciopiński

Kielce University of Technology

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Paweł Pięta

Kielce University of Technology

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Arkadiusz Chrobot

Kielce University of Technology

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Grzegorz Łukawski

Kielce University of Technology

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Mariusz Wisniewski

Kielce University of Technology

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Grzegorz Pawiński

Kielce University of Technology

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