Stefan Schürmans

Creation of ESL power models for communication architectures using automatic calibration

Power consumption is an important factor in chip design. The fundamental design decisions drawn during early design space exploration at electronic system level (ESL) have a large impact on the power consumption. This requires to estimate power already at ESL, which is usually not possible using standard ESL component libraries due to missing power models. This work proposes a methodology that allows extension of ESL models with a power model and to automatically calibrate it to match a power trace obtained by gate-level simulation or measurements. Two case studies show that the methodology is suitable even for complex communication architectures.

A compiler infrastructure for embedded heterogeneous MPSoCs

Programming heterogeneous MPSoCs (Multi-Processor Systems on Chip) is a grand challenge for embedded SoC providers and users today. In this paper, we argue the need for and significance of positioning the language and tool design from the perspective of practicality to address this challenge. We motivate, describe and justify such a practical design of a compilation framework for heterogeneous MPSoCs targeting the domain of streaming applications, named MAPS (MPSoC Application Programming Studio). MAPS defines a clean, light-weight C language extension to capture streaming programming models. A retargetable source-to-source compiler is developed to provide key capabilities to construct practical compilation frameworks for real-world, complex MPSoC platforms. Our results have shown that MAPS is a promising compiler infrastructure that enables programming of heterogeneous MPSoCs and increases productivity of MPSoC software developers.

Automatic calibration of streaming applications for software mapping exploration

This article investigates how to construct fast and accurate MPSoC virtual platforms to enable software mapping exploration. The proposed framework can fully automate the calibration of abstract MPSoC virtual platforms for mapping streaming applications.

ESL power estimation using virtual platforms with black box processor models

Processor models for electronic system level (ESL) simulations are usually provided by their vendors as binary object code. Those binaries appear as black boxes, which do not allow to observe their internals. This prevents the application of most existing ESL power estimation methodologies. To remedy this situation, this work presents an estimation methodology for the case of black box models. The evaluation for the ARM Cortex-A9 processor shows that the proposed approach is able to achieve a high accuracy. In comparison to hardware power measurements obtained from the OMAP4460 chip on the PandaBoard, the ESL estimation error is below 5%.

Black box power estimation for digital signal processors using virtual platforms

Complex many-core architectures are seen as the solution to tackle the computational workloads of the next years. To find the best trade-off between power and performance, different processor architectures have to be considered and evaluated in a thorough and power-aware design space exploration. This is highly facilitated by electronic system level (ESL) using virtual platforms. However, state-of-the-art methods of estimating power consumption require insight into the models of the platform. Or in case no insight is necessary, they are limited to only RISC architectures. The former requirement is in conflict with widely used proprietary models shipped as binary objects, i.e. black boxes. The methodology in this paper deals with both issues by enabling ESL black box power estimation for digital signal processors (DSP) using semi-automatic calibrated power models. Additionally, a case study reveals a high accuracy with a power estimation error of less than 4% for the Black-Fin 609 DSP on the FinBoard.

Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model

Power estimation has become a strongly desired feature in Electronic System Level (ESL) simulations. Most existing power estimation approaches for this abstraction level require component models with observable internals. However, most ESL models of modern processors are delivered as black box components. This work presents a tool-based ESL power estimation methodology for black box models and its extension for multiple clock frequencies. The evaluation uses hardware measurements of the ARM Cortex-A9 subsystem of the OMAP4460 chip for reference. The achieved estimation error is 5% on average for fixed-frequency power models and 7% for multifrequency power models.

Improving ESL power models using switching activity information from timed functional models

Early design space exploration at Electronic System Level (ESL) can be done either using untimed functional models, timed functional models or performance models, which use random or zero data instead of the actual data. In order to be applicable to the two latter types, ESL power estimation approaches often rely only on sub-block activity information. This work shows the benefit of additionally using the switching activity information of actual data available in timed functional models for power estimation. A case study shows that a considerable gain in accuracy can be achieved while causing only a moderate simulation slowdown.

Black box ESL power estimation for loosely-timed TLM models

Design space exploration (DSE) at system level needs to cover all parameters and has to find the best trade-off between performance and power of modern heterogeneous multi- and many-processor SoCs (MPSoC). Modelling virtual platforms with SystemC TLM offers fast HW and SW co-design using the loosely-timed (LT) coding style. However, simulations at this high abstraction level lack the capability of providing power estimates in case no insight into the models of the virtual platform is possible. This paper extends a well-proven black box power estimation methodology. The proposed method is capable of estimating the power with high accuracy using fast LT modelling. Two case studies reveal average estimation errors of just 5.1% and 3.5% for the ARM Cortex-A9 on the PandaBoard and the Blackfin 609 DSP on the FinBoard, respectively.

Towards Network Centric Development of Embedded Systems

Nowadays, the development of embedded system hardware and related system software is mostly carried out using virtual platform environments. The high level of modeling detail (hardware elements are partially modeled in a cycle-accurate fashion) is required for many core design tasks. At the same time, the high computational complexity of virtual platforms caused by the detailed level of simulation hinders their application for modeling large networks of embedded systems. In this paper, we propose the integration of virtual platforms with network simulations, combining the accuracy of virtual platforms with the versatility and scalability of network simulation tools. Forming such a hybrid toolchain facilitates the detailed analysis of embedded network systems and related important design aspects, such as resource effectiveness, prior to their actual deployment.

Automatic Calibration of Streaming Applications for Software Mapping Exploration

Streaming models have lately gained a lot of interest in embedded software design as they closely resemble computation of signal processing applications typically found in wireless and multimedia domains. To map streaming applications ontoMPSoCs (Multi-Processor System-on-Chips) efficiently, programmers need not only to validate software but also to estimate the performance of their software accurately. Therefore, fast MPSoC virtual platforms which support fully functional execution of software with good timing accuracy are required. In this paper, we propose a tool-flow to construct such MPSoC virtual platforms. The key idea is to annotate timing of sequential execution of streaming applications automatically by calibration in a configurable abstract MPSoC virtual platform. A case study of applying the tool-flow to a real-life heterogeneous MPSoC, TIs OMAP, has been conducted to prove the tool-flows feasibility and show good accuracy of the calibrated virtual platform for software mapping exploration.