Stefan Shopov

A 19 dBm, 15 Gbaud, 9 bit SOI CMOS Power-DAC Cell for High-Order QAM W-Band Transmitters

A mm-wave I-Q power-DAC is reported at W-band. The circuit, which is fabricated in a 45 nm SOI CMOS technology, employs a series-stacked Gilbert-cell output stage with gate finger geometry segmentation to directly modulate a 85-95 GHz carrier. The Gilbert-cell provides phase inversion and 7 bits for ASK envelope modulation, each of which can be switched at speeds up to 15 Gb/s. A ninth bit turns the entire DAC cell on and off at 15 Gb/s, as needed to create an arbitrary 15 Gbaud QAM constellation in a symmetrical 4×4 I-Q power-DAC transmitter array, with free-space power combining and antenna-level segmentation. The measured output power and PAE of the I or Q DAC cells are 19 dBm and 8.9%, respectively. Three effective bits of amplitude resolution and one phase bit are estimated from the small-signal S-parameter measurements in the 80-95 GHz range. The envelope amplitude resolution reduces to only two effective bits under saturated output power operation. The OOK bit provides over 45 dB of measured attenuation and dynamic range, relative to the peak output power.

A 234–261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4–7.2 dBm Output Power, 1.3% DC-to-RF Efficiency, and 1-GHz Divided-Down Output

A 234-261-GHz signal source with record 7.2-dBm output power at 240 GHz and -105 dBc/Hz phase noise at 10-MHz offset is reported. Fabricated in a production 55-nm SiGe BiCMOS process with HBT fT/fMAX of 330/350 GHz, the circuit includes a 120-GHz fundamental frequency VCO with 1.2-V AMOS varactors, a broadband MOS-HBT cascode LO tree driving a divide-by-128 chain, and a doubler with a record drain efficiency of 11.9%. The total power consumption of the signal source is 386 mW resulting in a DC-to-RF efficiency of 1.3%. A detailed discussion of the candidate LO-tree and doubler topologies and of the design methodology, which capitalizes on the MOS-HBT cascode and unique features of the 55-nm SiGe BiCMOS process, is provided.

Characterization of the High Frequency Performance of 28-nm UTBB FDSOI MOSFETs as a Function of Backgate Bias

This paper describes for the first time the high frequency performance characterization of a production 28-nm ultra-thin-body-and-BOX (UTBB) fully-depleted (FD) SOI CMOS technology. The measured g_m, f_T, and maximum available gain (MAG) of fully-wired n-channel and p-channel MOSFETs are reported as a function of gate-source, drainsource, back-gate voltages and drain current density. It is shown that the back-gate bias can reduce the V_GS at which the peak g_m, peak f_T and peak MAG occur by up to 400 mV and can flatten the f_T-V_GS characteristics, as needed in highly linear amplifiers. The peak g_m/f_T values of 1.5mS/μm/298GHz and 0.93mS/μm/194GHz, for n-MOSFETs and p-MOSFETs respectively, match or exceed those of 28-nm LP bulk and 45-nm SOI MOSFETs with identical layout geometry and metal stack wiring.

An 8-Bit 140-GHz Power-DAC Cell for IQ Transmitter Arrays with Antenna Segmentation

An 8-bit power-DAC cell is demonstrated for the first time at D-band in a production 45-nm SOI CMOS technology. The circuit proves the scalability of the transmitter array architecture with antenna segmentation from the W-band to the D-band. The last two stages of the power-DAC cell employ a novel two-stage common-gate Gilbert-cell topology with series-stacking to directly modulate a 125-144 GHz carrier in phase and in amplitude. The measured gain, saturated output power, and PAE of the power- DAC cell are 14.9 dB, 13.2 dBm, and 2.8%, respectively.

55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters

Two distributed circuits based on MOS-HBT cascodes are reported in a 55-nm SiGe BiCMOS technology and are aimed at a single-chip time-interleaved transceiver for future 1-Tb/s optical links. The first, a DC-135-GHz single-ended distributed amplifier (DA) was optimized for low noise, linear receivers, and has a measured noise figure (NF) <;7 dB up to 88.5 GHz, 800 mVpp of linear input range, and 8.5 dB gain. Operation was confirmed with PRBS-31 eye diagram measurements up to 120 Gb/s. Additionally, a novel time-interleaved distributed power DAC test circuit was implemented as a proof-of-concept to investigate the maximum achievable output bandwidth at a differential output voltage swing of 6 Vpp, as needed to directly drive an optical modulator. Simulations of the doubly segmented 6-bit DAC show 4-PAM output eye diagrams at up to 120 GBaud. The measured clock-input-to-data-output small-signal bandwidth is 65 GHz. When the DAC is measured as a switching large-swing driver, the differential output voltage swing remains larger than 5.4 Vpp beyond 50 Gb/s. Time interleaving of 4 thermometer MSBs is demonstrated experimentally to form a 1.8-Vpp differential, 10-GBaud 3-PAM output signal. The experimental sampling rate is limited to 10 GS/s by the capacitance and bandwidth of the low-frequency probes and pads used for the data lanes.

A 2×44Gb/s 110-GHz Wireless Transmitter with Direct Amplitude and Phase Modulation in 45-nm SOI CMOS

This paper investigates the maximum Baud rate and the scalability to the W-Band of the mm-wave IQ power-DAC transmitter architecture. A 45-nm SOI CMOS implementation achieves 44-Gbps BPSK and 88-Gbps BPSK+OOK modulation rates at 100-110 GHz with energy efficiency of 9.4 pJ/bit and output powers ranging from 8.6 to 11.7 dBm.

Analog Circuit Blocks for 80-GHz Bandwidth Frequency-Interleaved, Linear, Large-Swing Front-Ends

Critical analog electronic circuits for a possible 80-GHz bandwidth, frequency-interleaved, PAM-4 or discrete-multitone (DMT) linear fiber-optic front-end are implemented in a 90-nm SiGe BiCMOS technology. These include a novel vertically coupled, 40-100-GHz bandpass filter, an 80-GHz bandwidth distributed optical modulator driver with a measured output compression point of 13 dBm per side, corresponding to 7 Vpp output differential swing, and a 125-GHz bandwidth PIN-diode SPST switch with a OP1-dB of 23 dBm, and over 22 dB of isolation up to 160 GHz. The linear modulator driver can also be used as a high linearity (IP1-dB = 5 dBm per side) receiver amplifier in next-generation instrumentation systems.

A High Modulation Bandwidth, 110 GHz Power-DAC Cell for IQ Transmitter Arrays With Direct Amplitude and Phase Modulation

This paper studies the maximum Baud rate and the scalability to the W-Band of the mm-wave power-DAC transmitter architecture. Proof-of-concept implementations of a single DAC lane and of a 2×2 IQ transmitter array are reported in 45 nm SOI CMOS. The DAC cell achieved 29 GHz OOK and 29 GHz BPSK modulation bandwidth and 2×44 Gb/s BPSK+OOK data rates for carriers in the 100-110 GHz range. The corresponding energy efficiency is 7.5 pJ/bit at an output power of 12 dBm. For the 2×2 IQ array, an EVM of 9.0% is estimated over a 12 GHz bandwidth, from large signal power and S-parameter phase measurements.

A

A versatile three-lane transmitter/repeater array was designed and manufactured in a production 28nm ultra-thin body and BOX (UTBB) FD-SOI CMOS technology. Each lane in the array can operate at 60 Gb/s with adjustable output swing between 2.6 and 4.3 Vpp with a measured input sensitivity of 10 mVpp at 40 Gb/s, and requires at least 40mVpp input signal level to fully saturate the output driver for maximum swing operation at 60 Gb/s. Scaled, cascaded single-ended CMOS inverter transimpedance amplifiers with resistive and inductive feedback and interstage series inductive peaking were used to form the preamplifiers of each lane. These were optimized for maximum bandwidth and large gain, and drive the >4Vpp swing series-stacked cascoded CMOS inverter output stage. The single-ended CMOS-inverter topologies ensure that the total power consumption scales with the data rate and reduce the lane footprint to that of a ground-signal pad I/O. The measured lane-to-lane isolation is better than 40 dB up to 55 GHz, while the measured Tx-toRx dynamic range, defined as the ratio of the maximum output swing and corresponding minimum input voltage and sensitivity, is larger than 54 dB up to 40 Gb/s.

3\times 60\;\text{Gb/s}

This paper reviews the technology requirements of future mm-wave systems-on-chip and the challenges facing mm-wave MOSFET and SiGe HBT device and benchmark circuit scaling towards 3nm gate length and beyond 1.5THz fMAX. Measurements of state-of-the-art MOSFETs, HBTs and cascodes are presented from DC to 325 GHz. Finally, simulations of the scaling of the SiGe HBT mm-wave benchmark circuit performance across future technology nodes predict that PAs with 45% PAE at 220 GHz, and transimpedance amplifiers with over 175GHz bandwidth and less than 3dB noise figure will become feasible by the year 2030.