Steffen Ostendorff

A grid concept for reliable, flexible and robust remote engineering laboratories

Within this paper, we will describe a grid concept to realize a universal remote lab infrastructure as well as different operation modes based on this concept. This new infrastructure consists of three parts: an internal serial remote lab bus, a bus protection unit to interface the remote lab bus and to protect it from misuse and damage as well as a protection unit, which protects the physical systems (the electro-mechanical models in our remote lab) against deliberate damage or accidentally wrong control commands and which offers different access and control mechanisms. The interconnection between the Web-control units and the selected physical system during a remote lab work session (experiment) as well as the user management is done by the lab server, which also handles the webcams. The implemented remote lab infrastructure is based on the iLab architecture of the MIT, which allows to interconnect remote labs and to exchange remote lab experiments among different universities worldwide.

Using Interactive Hybrid Online Labs for rapid prototyping of digital systems

The Ilmenau Interactive Hybrid Online Lab offers several fields of application. In this article an enhancement of the existing Online Lab will be described to provide additional functionalities for a Web-based rapid prototyping of digital systems as well as the Web-based verification of such systems. For this new operation mode of the online lab a special rapid-prototyping board for digital systems was developed to fulfill the design tasks of digital systems. All the components of the rapid prototyping board will be described in detail. The implemented online lab infrastructure allows to interconnect online labs and to exchange remote lab experiments among different universities worldwide.

Automatic generation of an FPGA based embedded test system for printed circuit board testing

This paper describes an FPGA based embedded test system, designed for testing of printed circuit boards during the manufacturing process. The test system architecture is automatically generated based on a layer description, which provides the required flexibility for the generation of the test system, and for the abstraction of the test functions. The test system is composed of a software and a hardware part, and generated based on the boards properties and the specified test algorithms. The paper presents the test system architecture and automatic generation flow, with emphasis on the software generation process. The paper also includes experimental results obtained when performing an SRAM interconnection test.

A Concept for a Flexible and Scalable Infrastructure for Remote Laboratories

This paper describes a universal remote lab infrastructure. This new extended infrastructure consists of three parts: a control unit for performing practical experiments with the physical systems, located in our remote lab, a bus protection unit to interface the remote lab bus and to protect it from misuse and damage, as well as a protection unit, which protects the physical systems against deliberate damage or accidentally wrong control commands. These units are for control, interface, surveillance and protection of the connected physical systems. The general concept and setup is presented in this paper, including the possibilities and limitations of such an approach. This concept is an extension of the remote lab architecture proposed in earlier papers.

A new approach for adaptive failure diagnostics based on emulation test

The paper describes a new approach of boundary scan emulation based testing for adaptive failure diagnostics using programmable logic. The motivation to speed up boundary scan based testing as well as the approach taken for this new concept and architecture are presented. With this approach the possibilities of boundary scan testing can be extended by using the available on-board resources for a faster and more real-time oriented test. The new options and benefits, as well as the necessary fundamentals of this approach are indicated. An example and first test results are given as well, to indicate the advantage of the proposed system.

Architecture of an adaptive test system built on FPGAs

This paper describes an FPGA based test system, designed to improve current board level test methods such as boundary scan. The design of the system architecture is based on a layer concept that provides important advantages for its flexibility. This makes it possible to reconfigure and automatically generate the test system determined by the boards properties and the specific test algorithms. The principal system components are a soft-processor equipped with debug and communication functions, and co-processing units built from component models. The system architecture and its relation to the layer concept are presented, mentioning basic properties such as FPGA vendor independency and JTAG compatibility.

Mobile Prototyping Platforms for Remote Engineering Applications

This paper describes a low-cost mobile communication platform as a universal rapid-prototyping system, which is based on the Quadrocopter concept. At the Integrated Hardware and Software Systems Group at the Ilmenau University of Technology these mobile platforms are used to motivate bachelor and master students to study Computer Engineering sciences. This could be done by increasing their interest in technical issues, using this platform as integral part of a new ad-hoc lab to demonstrate different aspects in the area of Mobile Communication as well as universal rapid prototyping nodes to investigate different mechanisms for self-organized mobile communication systems within the International Graduate School on Mobile Communications. Beside the three fields of application, the paper describes the current architecture concept of the mobile prototyping platform as well as the chosen control mechanism and the assigned sensor systems to fulfill all the required tasks.

Modeling timing constraints for automatic generation of embedded test instruments

This paper describes a new method to model timing constraints for the generation of basic control functions for embedded test instruments in the area of structural testing of printed circuit boards. It describes how the timing information is extracted from data sheets, modeled in a domain specific language and processed to obtain the shortest possible test time for the automatically generated embedded test instrument. The generated hardware description of the test instrument is supplied as a co-processor to an embedded test-processor. This enables the processor to access the devices-under-test with correct and optimal timing, to speed up the test process and to allow at-speed testing.

ISA configurability of an FPGA test-processor used for board-level interconnection testing

This paper presents a study of FPGA test-processor configurability at the instruction set architecture (ISA) level used for board-level interconnection testing. The ISA configurability is used as adaptation mechanism to the test requirements, the FPGA properties, and the devices under test (DUTs). The aim is to show the advantages and limitations of processor configurability at this level, and demonstrate them in the FPGA based test system (FBTS) developed for board-level interconnection testing. The paper presents the test-processors concept, adaptation aspects, and architecture, followed by experimental results performed with different processor configurations. Results show the advantages of having a configurable test-processor in terms of performance and FPGA resource utilization.

Test Pattern Dependent FPGA Based System Architecture for JTAG Tests

The paper describes a new approach to speed-up and improve boundary scan based testing, by assigning functionality to a layer concept implemented in programmable logic. The motivation is driven by the constantly increasing gap between available and testable functionality of printed circuit boards. The motivation, architecture and build process of the proposed test and validation system is presented. Furthermore one selected example and first results are given to indicate the advantage of the proposed concept.