Stephan G. Meier

A seventh-generation x86 microprocessor

An out-of-order, three-way superscalar /spl times/86 microprocessor with a 15-stage pipeline, organized to allow 600 MHz operation, can fetch, decode, and retire up to three /spl times/86 instructions per cycle to independent integer and floating-point schedulers. The schedulers can simultaneously dispatch up to nine operations to seven integer and three floating-point execution resources. A sophisticated, cell-based design technique and judicious application of custom circuitry permit the development of a processor with an aggressive architecture and high clock frequency with a rapid design cycle. Design-for-test techniques such as scan and clock bypassing permit straightforward testing and debugging of the part.

An out-of-order three-way superscalar multimedia floating-point unit

The AMD-K7/sup TM/ floating point unit is implemented as an out-of-order coprocessor responsible for executing all x86 FPU, MMX/sup TM/, and AMD 3DNoW!/sup TM/ instructions. The FPU interfaces to the AMD-K7 core, which sends it instructions, load data, and guides the retirement of instructions. The FPU sends store data and completion status back to the core. The FPU contains 2.4 M transistors on a 10.5/spl times/2.6 mm/sup 2/ die in a 0.25 /spl mu/m process. A micrograph of the FPU is shown.