Stephen R. Gilbert

Preparation of Pb(Zr,Ti)O3 thin films by metalorganic chemical vapor deposition for low voltage ferroelectric memory

To realize the full potential of high density embedded ferroelectric memory, ferroelectric film thickness must be scaled below 100 nm to ensure that the capacitor operating voltage is compatible with advanced, low voltage logic transistors. In this article, we describe recent progress in the preparation of sub-100 nm thick Pb(Zr,Ti)O3 (PZT) thin films by metalorganic chemical vapor deposition on 200 mm wafers using an industry-standard processing platform. Within the full range of thicknesses investigated, 134–52 nm, capacitor operating voltage scales linearly with film thickness, yielding 71 nm thick films with a switched polarization (Psw) of ∼40 μC/cm2 at 1.2 V. Below ∼50 nm, PZT surface roughness makes further thickness scaling difficult. With improved surface morphology, however, even lower operating voltages should be feasible.

Demonstration of scaled (≥0.12 μm2) Pb(Zr, Ti)O3 capacitors on W plugs with Al interconnect

The measured switched polarization properties of integrated Pb(Zr,Ti)O3 (PZT) capacitors arrays have been found to show a small dependence on individual capacitor size in the range from 0.17 and 100 μm2. These thin (90 nm) PZT capacitors have low voltage switching properties with polarization saturation of <1.8 V with switched polarization for the smallest capacitors (0.17 μm2) still larger than 25 μC/cm2. The capacitor stack consisted of TiAlN hardmask/Ir/IrOx/PZT/Ir/TiAlN on either SiO2 dielectric or W plugs. The capacitor was patterned using 248 nm lithography and etched using only one mask. For wafers without W plugs, the Ir bottom electrode was not etched. For wafers with W plugs, the entire capacitor stack was etched and electrical connection to the bottom electrode was through the W plugs. The capacitors were integrated using SiO2 dielectrics and one level of Al metallization. These data suggest that high-density, ferroelectric capacitor-based memories may be feasible.

Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process

We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.

Deuterium-induced degradation of (Ba, Sr)TiO3 films

Electrical degradation of (Ba, Sr)TiO3 (BST) thin films was investigated by annealing Pt/BST/Pt structures in D2/N2 and D2O-containing furnace ambients. Deuterium depth profiles were correlated to the current–voltage characteristics of the BST thin films. The dependence of the D distribution and leakage current density on the D incorporation method indicates that mobile, donor-type deuterium defects dissolve in large concentrations within BST thin films, and that their effects on leakage properties depend on the nature of their charge compensation. A mechanism is proposed for the leakage current increase after D2/N2 anneals, and good quantitative agreement between the theoretical results and experimental data is demonstrated.

PZT material properties at UHF and microwave frequencies derived from FBAR measurements

Lead zirconate titanate (PZT) is a high dielectric constant, /spl epsiv//sub r//sup S/, high coupling, k/sub t//sup 2/, piezoelectric material with possible application to film bulk acoustic resonators (FBAR) at low microwave frequencies. PZT is a widely used material at audio and low MHz range frequencies, but the high acoustic attenuation of PZT tends to preclude its use above UHF. Likewise, the bulk dielectric/piezoelectric/elastic (DPE) properties are well known at low frequencies, but the thin film properties have not been as well measured into the microwave range. To obtain better data, the material properties of thin film PZT deposited by several methods were measured at GHz frequencies from air- or silicon-backed FBARs fabricated on silicon wafers. PZT thin films, deposited by metal-organic chemical vapor deposition (MOCVD), sol-gel deposition, RF sputtering, or jet vapor deposition, were obtained from various sources. The films examined ranged from 0.4 to 2 /spl mu/m in thickness, and were deposited on thin (/spl sim/0.1 /spl mu/m) Pt or Ir bottom electrodes. The samples had compositions within the tetragonal phase (Zr/Ti = 30/70, 40/60) or near the morphotropic phase boundary (Zr/Ti = 50/50). Scattering parameter, S/sub 11/, vs frequency measurements were made. Using the Mason equivalent circuit model, the DPE coefficients were extracted by varying parameters in the Mason model until the predicted S/sub 11/ vs frequency fitted the measured data. The devices exhibited /spl epsiv//sub r//sup S/ in the range of 300 to 500, k/sub t//sup 2/ between 5% and 35%, and acoustic attenuation from 400 to 2100 dB/cm at 1 GHz.

Deuterium in (Ba,Sr)TiO3 thin films: Kinetics and mechanisms of incorporation and removal during annealing

The kinetics of deuterium doping of and removal from polycrystalline (Ba,Sr)TiO3 (BST) thin films during annealing were investigated using secondary ion mass spectrometry depth profiling, and the data were correlated to changes in the electrical behavior of the films. Results for deuterium doping of exposed BST films on a Pt bottom electrode layer are consistent with incorporation of deuterium interstitial defects at the BST/Pt interface and “upward” diffusion toward the film surface. The incorporation kinetics of deuterium in Pt/BST/Pt capacitors are more complex and are greatly enhanced by the presence of the Pt top electrode. Removal of deuterium from D2/N2-exposed Pt/BST/Pt specimens during oxygen recovery anneals appears to be limited by the rate of an interfacial reaction at low temperatures (200–250 °C). The pre-D2 exposure leakage current properties of the BST capacitors were found to be largely recovered when the deuterium concentration in the films was reduced to ∼1019 cm−3 during post-D2 oxygen...

Hydrogen-Robust Submicron IrOx/Pb(Zr, Ti)O3/Ir Capacitors for Embedded Ferroelectric Memory

We have demonstrated that the scaling of IrOx (Pb(Zr, Ti)O3:PZT)/Ir capacitors can be extended into the submicron regime. The submicron IrOx /PZT/Ir capacitors were fabricated using a one-mask stack-etch process, integrated with an SiO 2 interlayer dielectric, and contacted with Al metallization. The aggregate electrical properties of integrated PZT capacitor arrays are shown to be nearly independent of individual capacitor area in the range between 10 2 µm 2 and 0.12µm 2 . In particular, switched polarization values of more than 30µC/cm 2 were obtained for PZT capacitors with an individual capacitor area of 0.12 µm 2 . This result suggests that the lateral scaling can be achieved down to 0.1 µm 2 . Through the use of appropriate diffusion barriers, hydrogen-robust submicron PZT capacitors are obtained. No degradation in ferroelectric properties of submicron PZT capacitors was observed under the test conditions. These results suggest that PZT capacitors can be integrated into a standard complementary metal oxide semiconductor (CMOS) process flow with minimal degradation.

Oxygen tracer studies of ferroelectric fatigue in Pb(Zr, Ti)O3 thin films

Long-range oxygen motion has been observed in Pt/Pb(Zr,Ti)O3/Ir thin-film structures after electrical fatigue cycling at room temperature. Through an exchange anneal, isotopic 18O was incorporated as a tracer into bare Pb(Zr,Ti)O3 (PZT) films, allowing secondary ion mass spectrometry measurements of the tracer profile evolution as a function of the number of polarization reversals. Observation of 18O tracer redistribution during voltage cycling, which is presumably mediated by oxygen vacancy motion, was found to be strongly dependent upon the thermal history of the film. However, there was no strong correlation between the extent of 18O tracer redistribution and the extent of polarization suppression induced by voltage cycling. Our results suggest that oxygen vacancy motion plays, at most, a secondary role in ferroelectric fatigue of PZT thin films.

A low noise 1.5GHz VCO with a 3.75% tuning range using coupled FBAR's

We present the first IC oscillator using acoustically coupled FBARs with a 3.75% tuning range. The tuning range is higher than previous low-power FBAR oscillators and wide enough to cover the individual ISM bands. The high Q of the resonator enables to achieve a phase noise of -144.35dBc/Hz at 1MHz offset with a carrier frequency of 1.55GHz and a power consumption of 11.7mW. The miniaturized coupled FBAR die is (500×540)μm2. The active area of the CMOS is (600x550)μm2.

Cross-Contamination during Ferroelectric Nonvolatile Memory Fabrication

New metal contaminants, such as Pb, Zr, and Ir, introduced during ferroelectric nonvolatile memory (FeRAM) fabrication are of great concern hecause of their potentially adverse effects on complementary metal oxide semiconductor device characteristics. Numerous routes for cross-contamination exist in a Si wafer fab. In this study, we focus on the transfer of elements between the contaminated wafer handling system of a typical shared tool and the back side of clean wafers. Specifically, the potential for transferring Pb, Zr, Ti, and Ir from a contaminated surface to clean wafers was investigated. It was found that, after exposing a robotic handler and chuck directly to the surface of Pb(Zr,Ti)O 3 films, clean wafers that were subsequently run through the tool acquired a maximum of 1.1 × 10 11 , 9.0 × 10 10 , and 5.1 × 10 10 atoms/cm 2 of Pb, Zr, and Ti, respectively. After exposing the tool to Ir films, significantly less Ir transferal was observed (1.0 X 10 9 atoms/cm 2 ). In all cases, cycling a series of clean wafers through the tool led to a rapid decrease in the quantity of transferred contaminants, and was the most effective method for eliminating these elements altogether. Moreover, the Pb, Zr, Ti, or Ir contaminants transferred in this way were easily removed using a traditional pregate surface cleaning process.