Steve Wilton

An energy and power consumption analysis of FPGA routing architectures

In this work, we evaluate bi-directional and unidirectional FPGA routing architectures in terms of energy and power consumption using an updated power estimation framework compatible with VPR 5.0. The goal of this research is to help FPGA vendors find the best FPGA architectures. Initially, we make some general observations on how two types of routing architectures affect speed, area consumption, and power consumption. We observe how routing buffer sizing affects both the critical path delay and power and energy consumption of FPGAs with certain routing architectures. Our results show that uni-directional routing architecture, in all but one case, is the most energy efficient choice both in the traditional FPGA domain and the mobile domain where clock frequencies are fixed.

Self-hosted placement for massively parallel processor arrays

We consider the placement problem as part of the CAD flow for a massively parallel processor arrays (MPPAs). In contrast to traditional placers, which operate on a workstation with one or several cores and are able to take advantage of parallelism to a limited degree, we investigate running the placer on the target architecture itself. As the number of processor elements (PEs) in such a device scale, so too does the computational power available to the placer. This natural scaling helps avoid the long runtimes that afflict FPGA flows.

Congestion-driven regional re-clustering for low-cost FPGAs

FPGA device area is dominated by a limited amount of interconnect. CAD tools must meet a hard channel-width constraint for a circuit to be successfully mapped to a device. Previous work has shown that if a design cannot be mapped to a device due to insufficient interconnect availability, it is possible to identify regions of high interconnect demand and spread out the logic in this area into surrounding regions. This is done by re-packing logic in the affected regions into an increased number of CLBs. This increases the effective amount of interconnect in these high-demand areas. This methodology has been shown to significantly reduce channel width, at the expense of CLB count and runtime. In this paper, we extend this previous algorithm in two ways: we present novel region selection techniques to optimize the selection of which regions should be depopulated, and we introduce a local channel-width demand model which can be used to more accurately determine the amount of white space insertion at each iteration. Together, these techniques lead to significant run-time improvements and reduce the area of the resulting FPGA implementations. We were able to improve runtime by a factor of up to 5.5 times while reducing area by up to 20% when compared to previous methods.

Embedding of quantum-dot cellular automata circuits onto a quantum annealing processor

Simulations of quantum-dot cellular automata (QCA) on classical computers are highly limited due to the exponential growth in resources required for the numerical simulation of quantum mechanics involving networks of finite state nodes. Recent advancements in computing based on networks of flux-qubits, and in particular the platform technology developed by D-Wave Systems Inc., have made it possible to explore QCA networks that are intractable on classical machines. However, the embedding of such networks onto the available processor architecture is a key challenge in setting up such simulations. In this work, two approaches to embedding QCA circuits are characterized: a dense placement algorithm that uses a routing method based on negotiated congestion; and a heuristic method implemented in D-Waves SAPI package. Both embedding methods are characterized using a set of basic QCA benchmark circuits of various sizes and complexities. When including diagonal interactions only in the case of an inverter, both methods were able to embed a 4-bit 2-1 multiplexer circuit containing 192 non-driver QCA cells onto the 512 qubit D-Wave Vesuvius chip architecture. Including diagonal interactions for all cells, both methods successfully embedded a serial adder circuit containing 126 non-driver cells.

SoC architectures for signal processing

This session explores different architectures, fabrics, and interconnect structures for signal processing and computing. These structures range from general purpose, domain specific, to application specific. These papers consider power, throughput, and flexibility trade-offs.This session explores different architectures, fabrics, and interconnect structures for signal processing and computing. These structures range from general purpose, domain specific, to application specific. These papers consider power, throughput, and flexibility trade-offs.