Steven F. Gillig

A 14 b 100 Msample/s CMOS DAC designed for spectral performance

At 60 MSample/s, DAC SFDR is 80 dB for 5.1 MHz input signals and is down only to 75 dB for 25.5 MHz input signals. Previous DACs specified for operation at this speed and resolution have exhibited similar SFDR only at lower clock and/or signal frequencies. The DAC is implemented in a 0.8 /spl mu/m CMOS process (minimum gate length is 0.65 /spl mu/m), consumes 750 mW at 100 MSample/s speed, and utilizes a special output stage circuit to obtain dynamic performance.

A carry-free 54b/spl times/54b multiplier using equivalent bit conversion algorithm

An equivalent bit conversion algorithm (EBCA) is proposed to eliminate the need for final carry propagation in the redundant binary (RB) to normal binary (NB) conversion step for RB multiplication. The multiplication process helps with the carry-free conversion step by eliminating certain combinations of RB product. When the EBCA is applied, conventional power-consuming carry-propagating adders are replaced by simple, minimum-sized carry-free converters, and the entire multiplication process can be made free of carry propagation from input to output. The method employed in this work reduces 40% of the total power and 30% of the total multiplication time in the final adder stage of traditional multipliers. The prototype fabricated in 0.35-/spl mu/m CMOS demonstrates that the 54 b/spl times/54 b multiplier consumes only 53.4 mW at 3.3 V for 74-MHz operation.

A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC

CMOS analog-to-digital converters (ADCs) require either bootstrapping techniques or low-threshold devices to function at low supply voltages. A 6-b 50-MSamples/s ADC in normal-threshold CMOS operates with a single battery cell as low as 0.9 V without bootstrapping. A current-interpolation approach is taken to configure a 1-V ADC system that does not allow more than one V/sub GS/ plus one V/sub DSsat/ between the supply rails. The prototype takes a rail-to-rail input and works with a single system clock. The chip fabricated in 0.35-/spl mu/m CMOS occupies an area of 2.4/spl times/2 mm/sup 2/ and consumes 10 mW each in analog and digital supplies.

Method and means of detecting the presence of a signal representing voice and of compressing the level of the signal

A circuit that combines the functions of audio compression and voice detection comprises an amplifier in a negative-feedback configuration in which the feedback signal is the product of the output of the amplifier and a syllabic voltage derived from that output. The syllabic voltage is compared with a threshold level to provide an output that is a measure of the presence of a voice signal. In an alternate embodiment, the syllabic voltage is compared with the sum of a threshold level and a detected syllabic voltage to generate a signal that is a measure of the presence of voice. The syllabic detector may be either an averaging detector or a valley detector.

A 1 V 6 b 50 MHz current-interpolating CMOS ADC

A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.