Steven Fong

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Publication

Featured researches published by Steven Fong.

Archive | 1999

Floating gate memory apparatus and method for selected programming thereof

Stewart Logie; Sunil D. Mehta; Steven Fong

Archive | 1999

Zero-power CMOS non-volatile memory cell having an avalanche injection element

Sunil D. Mehta; Brad Sharpe-Geisler; Steven Fong

Archive | 1999

Avalanche injection EEPROM memory cell with P-type control gate

Xiao-Yu Li; Steven Fong; Sunil D. Mehta

Archive | 1999

Pmos avalanche programmed floating gate memory cell structure

Steven Fong; Stewart Logie; Sunil D. Mehta

Archive | 2000

Complementary avalanche injection EEPROM cell

Sunil D. Mehta; Steven Fong; Stewart Logie

Archive | 2009

Shallow trench isolation (STI) with trench liner of increased thickness

Sunil D. Mehta; Stewart Logie; Steven Fong

Archive | 2011

Simultaneous development of complementary IC families

Shawn Murray; John Schadt; Steven Fong; Luan Phoc Chau; Thomas R. Gustafson

Archive | 2006

Process for fabricating a semiconductor device having an RTCVD layer

Sunil D. Mehta; Steven Fong; Yongzhong Hu

Archive | 2005

Diode structure for word-line protection in a memory circuit

Fabiano Fontana; Steven Fong; Sunil D. Mehta; Yongzhong Hu

Archive | 2005

Procede destine a fabriquer un dispositif a semi-conducteur comprenant une couche rtcvd

Sunil D. Mehta; Steven Fong; Yongzhong Hu

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Collaboration

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Sunil D. Mehta

Advanced Micro Devices

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Stewart Logie

Advanced Micro Devices

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Top Co-Authors

Xiao-Yu Li

Advanced Micro Devices

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Lattice Semiconductor

Archive Network Publication Hotspot Collaboration

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot

Dive into the research topics where Steven Fong is active.

Publication

Featured researches published by Steven Fong.

Floating gate memory apparatus and method for selected programming thereof

Zero-power CMOS non-volatile memory cell having an avalanche injection element

Avalanche injection EEPROM memory cell with P-type control gate

Pmos avalanche programmed floating gate memory cell structure

Complementary avalanche injection EEPROM cell

Shallow trench isolation (STI) with trench liner of increased thickness

Simultaneous development of complementary IC families

Process for fabricating a semiconductor device having an RTCVD layer

Diode structure for word-line protection in a memory circuit

Procede destine a fabriquer un dispositif a semi-conducteur comprenant une couche rtcvd

Collaboration

Dive into the Steven Fong's collaboration.