Steven Neal Renfrow

High sensitivity impurity measurements in semiconductors using trace-element accelerator mass spectrometry (TEAMS)

Trace-Element Accelerator Mass Spectrometry (TEAMS) is the extension of conventional radioisotope Accelerator Mass Spectrometry to the measurement of very low-levels of stable isotopes. The primary application of TEAMS is in the field of materials analysis, particularly semiconductors, where it offers the potential for measuring trace impurities at concentration levels as low as a few parts per trillion (ppt). The Ion Beam Modification and Analysis Laboratory at the the University of North Texas has built a dedicated facility for TEAMS measurements. This paper describes recent modifications and improvements to the system and shows results of some recent measurements.

Materials Analysis using Trace Element Accelerator Mass Spectrometry (TEAMS)

The Ion Beam Modification and Analysis Laboratory (IBMAL) at the University of North Texas has set up a dedicated Trace-Element Accelerator Mass Spectrometry (TEAMS) system for low-level impurity measurements. TEAMS has previously shown the ability to measure impurity copper levels in silicon wafers with a better sensitivity than Secondary Ion Mass Spectrometry (SIMS), one of the most sensitive measurement techniques. TEAMS is especially suited for bulk measurements of low levels of impurities in materials. A discussion of some of the issues involved in TEAMS measurements is presented along with the results of impurity iron measurements in silicon.

Ion induced electron emission from Si and photoresist surfaces

Ion induced electron emission (IIEE) from solid surfaces is one of the fundamental processes with ion beam applications. The different IIEE yields from different surfaces such as Si, SiO2, metals and photoresist (PR) may cause charging and damage the gate oxide in ion implantation. IIEE yields with B+ and Si+ beams were measured for several kinds of PR materials, bare and oxide wafers. Although the target chamber pressure was always in or below the low 10−7 Torr range, the IIEE yield from PR surfaces was found to be a function of implant dose with the most dramatic change in the beginning of implantation. For other materials such as Si and SiO2, the IIEE yield is independent of implant dose after the initial variation due to surface contamination.

Ion beam induced charge collection (IBICC) from integrated circuit test structures using a 10 MeV carbon microbeam

As future sizes of Integrated Circuits (ICs) continue to shrink the sensitivity of these devices, particularly SRAMs and DRAMs, to natural radiation is increasing. In this paper, the Ion Beam Induced Charge Collection (IBICC) technique is utilized to simulate neutron-induced Si recoil effects in ICS. The IBICC measurements, conducted at the Sandia National Laboratories employed a 10 MeV carbon microbeam with 1pm diameter spot to scan test structures on specifically designed ICS. With the aid of layout information, an analysis of the charge collection efficiency from different test areas is presented. In the present work a 10 MeV Carbon high-resolution microbeam was used to demonstrate the differential charge collection efficiency in ICS with the aid of the IC design Information. When ions strike outside the FET, the charge was only measured on the outer ring, and decreased with strike distance from this diode. When ions directly strike the inner and ring diodes, the collected charge was localized to these diodes. The charge for ions striking the gate region was shared between the inner and ring diodes. I The IBICC measurements directly confirmed the interpretations made in the earlier work.

ION BEAM INDUCED CHARGE COLLECTION (IBICC) OF INTEGRATED CIRCUITS USING A 10 MEV CARBON MICROBEAM

Abstract This paper presents ion beam induced charge collection (IBICC) data that simulates cosmic neutron-induced Si recoil effects in IC test structures. The experiments, conducted at Sandia National Laboratories, employed a 10 MeV Carbon microbeam with 1 μm diameter spot to scan test structure on specifically designed ICs. The test structure contains junctions typical of SRAMs and DRAMs. With the aid of IC layout information, an analysis of the charge collection efficiency from different test areas is given.