Steven S. Hegedus

Current–Voltage Analysis of a-Si and a-SiGe Solar Cells Including Voltage-dependent Photocurrent Collection

The current–voltage (J(V)) data measured in light and dark from a-Si-based solar cells have been analyzed to yield six parameters that completely specify the illuminated J(V) curve from reverse bias to beyond open-circuit voltage (Voc). A simple photocurrent collection model is used, which assumes drift collection in a uniform field. The method has been applied to J(V) data from over 20 single-junction a-Si or a-SiGe devices from five laboratories measured under standard simulated sunlight. Very good agreement is obtained between measured and calculated J(V) performance with only one adjustable parameter, the ratio of collection length to thickness Lc/D. Some of these devices have also been analyzed after extended light soaking or under filtered illumination. The effect of the voltage-dependent photocurrent collection on the fill factor and Voc is considered in detail. Results under 1 sun illumination for both a-Si and a-SiGe devices are consistent with hole-limited collection. Photocurrent collection in very thin devices (D ∼ 0.1 μm), or thicker devices under blue light, may be strongly influenced by interface recombination or back diffusion. The flatband voltage (Vfb) is dependent on the intensity and spectrum of illumination, and hence is not a fundamental device property and is not equivalent to the built-in potential. The Voc is limited by Vfb, not junction recombination current Jo, in typical devices. The illuminated solar cell performance is nearly independent of the forward diode current for low values of Lc/D, as occurs after light soaking or with a-SiGe. The model is also useful to investigate the intensity dependence of the fill factor and to predict the influence of Lc/D and Vfb on solar cell performance.

EFFECTS OF PROCESSING ON CdTe/CdS MATERIALS AND DEVICES

By analyzing CdTe/CdS devices fabricated by vacuum evaporation, a self consistent picture of the effects of processing on the evolution of CdTe cells is developed which can be applied to other fabrication methods. In fabricating CdTe/CdS solar cells by evaporation, a 400°C CdCI2 heat treatment is used which recrystallizes the CdTe and interdiffuses the CdS and CdTe layers. The interdiffuson can change the bandgap of both the CdTe and CdS which modifies the spectral response of the solar cell. After this heat treatment a contacting/doping procedure is used which converts the CdTe conductivity to p-type by diffusion from Cu from the contact. Finally, the cell is treated with Br2CH3,OH which improves both Voc and FF. Analogous process steps are used in most fabrication processes for CdTe/CdS solar cells.

Improved fill factors in amorphous silicon solar cells on zinc oxide by insertion of a germanium layer to block impurity incorporation

Amorphous silicon based solar cells deposited on zinc oxide (ZnO) exhibit reduced fill factor and open circuit voltage in comparison with tin oxide (SnO2). One approach has been to use higher conductivity nanocrystalline layers to overcome the “higher contact resistance.” Recent measurements have found the ZnO–p-layer contact resistance to be unchanged relative to SnO2, while instead, the diode ideality factor is poorer on ZnO. We show that the insertion of a thin, amorphous germanium layer at the ZnO–p-layer interface improves the cell performance and diode ideality factor by suppression of oxygen and zinc incorporation in the silicon layers.

Correlation of surface phases with electrical behavior in thin-film CdTe devices

Glancing incidence X-ray diffraction (GIXRD) analysis of crystalline surface phases in cadmium telluride solar cells is correlated with device behavior for different processing conditions. GIXRD sampling depths are calculated for different phases and X-ray sources. Air heat treatment of CdTe films forms the native oxide CdTeO , while treatment in CdCl yair vapor forms 32 CdTeO and CdO. Air treatment followed by CdCl yair treatment forms surface oxides, reduces CdS diffusion into CdTe and 32 improves junction performance. The CdTeO surface oxide limits CdCl concentration in the CdTe film, yet allows sufficient 32 CdCl species for CdTeyCdS junction activation. In devices, residual oxide phases contribute to series resistance and current– 2 voltage retrace hysteresis. These effects are mitigated by oxide removal and formation of a Te layer. Addition of Cu to the contact followed by thermal treatment increases open circuit voltage. Optimal cell performance is obtained for Cu y(CuqTe) atomic ratios0.7. 2003 Elsevier Science B.V. All rights reserved.

Midgap states in a‐Si:H and a‐SiGe:H p‐i‐n solar cells and Schottky junctions by capacitance techniques

The midgap density of states (MGDOS) in a‐SiGe:H alloys is investigated by capacitance measurements on p‐i‐n solar cells. Past work on thick a‐Si:H Schottky barriers is extended to thin a‐SiGe:H p‐i‐n cells. Four methods of determining the MGDOS from the measured capacitance are described, and each is applied to two p‐i‐n devices having 0% and 62% Ge in the i layers, respectively. The first method involves fitting an equivalent circuit model to the measured admittance. Close agreement is found over a wide range of temperature and frequency. The single junction model is shown to apply equally well to p‐i‐n and Schottky diodes, justifying the neglect of the n‐i junction and thin doped layers in the p‐i‐n admittance analysis. A second method determines g0 from the limiting capacitance at high temperature. The third and fourth methods extract g0 from the dependence of capacitance on voltage bias. One of these is novel, presented here for the first time. Thus, a unique feature of this study is the application ...

The relation of dark and illuminated diode parameters to the open‐circuit voltage of amorphous silicon p‐i‐n solar cells

We have measured the current‐voltage characteristics of a‐Si:H p‐i‐n solar cells having open‐circuit voltages (Voc) between 0.70 and 0.90 V as a function of temperature and light intensity. The diode parameters (diode factor, saturation current density, and built‐in voltage) were calculated in the light and in the dark. We find that parameters obtained in the dark have no relevance to the analysis of Voc, but they do indicate that tunneling may be a significant effect in the dark. The Voc is dominated by recombination at the p/i interface or in the i layer near this interface. Reducing interface recombination with a carbon buffer layer and reducing bulk recombination with less i layer impurities improves Voc by reducing the forward recombination current density.

Analysis of stress-induced degradation in CdS/CdTe solar cells

Accelerated stressing of CdS/CdTe solar cells at elevated temperatures (60-100/spl deg/C) under a range of applied bias in light and dark has identified three degradation modes: formation of a blocking contact, increased junction recombination, and increased dark resistivity. Devices with Cu-contacts degrade with a strong bias dependence. The blocking contact is formed under forward bias. Junction degradation requires both higher temperature and forward bias. Recontacting the device after stress removes the blocking contact with no change in junction losses. Devices without Cu in the contact have much poorer initial performance but degrade nearly independent of bias.

Novel photochemical vapor deposition reactor for amorphous silicon solar cell deposition

A novel photochemical vapor deposition (photo‐CVD) reactor having a flexible ultraviolet‐transparent Teflon curtain and a secondary gas flow to eliminate deposition on the window has been used to deposit amorphous silicon films and p‐i‐n solar cells. The background levels of atmospheric contaminants (H2O, CO2, N2) depend strongly on the vacuum procedures but not on the presence of a Teflon curtain in the reactor. Intrinsic films with a midgap density of states of 3×1015 eV−1 cm−3 and all‐photo‐CVD pin solar cells with efficiencies of 8.5% have been deposited.

Investigation of hetero-interface and junction properties in silicon heterojunction solar cells

The amorphous silicon (a-Si:H) - crystalline silicon (c-Si) heterojunction (SHJ) solar cell fill factor (FF) is very sensitive to the properties of c-Si surface, process parameters of thin a-Si:H layers, properties of transparent conducting front electrode, and all of their interfaces. In this work, quality of hetero-interface and junction properties in n-type SHJ solar cells were investigated by; (i) suns VOC under white, blue, and infrared light; (ii) dark and light JV; and (iii) quantum efficiency (QE) with and without voltage and light bias. Analysis of all these measurements suggest an anomalous “S” shape JV curve can arise due to at least two separate reasons; (a) existence of a large barrier for hole transport with excellent front surface passivation, and (b) existence of an opposing diode/Schottky barrier in the hetero emitter side of a SHJ solar cell. Both of the above-mentioned interface and/or junction properties severely affect minority carrier collection in SHJ cells.

Alternative approaches for low temperature front surface passivation of interdigitated back contact silicon heterojunction solar cell

In this work, we investigated two alternative approaches for the front surface passivation of interdigitated back contact silicon heterojunction (IBC-SHJ) solar cells: (1) with plasma enhanced chemical vapor deposited (PEVCD) a-Si-based stack structure consisting of a-Si:H/a-SiNx:H/a-SiC:H, and (2) with physical vapor deposited (PVD) zinc sulfide (ZnS) film. The processing temperatures for both the approaches are under 300°C. Effective surface recombination velocities (SRV) of < 6.2cm/s and < 35cm/s are obtained with stack structure and ZnS respectively on n-type float zone (FZ) crystalline silicon (c-Si) wafers. The anti-reflection (AR) properties of these two passivation approaches are studied and the optimization procedure of the stack structure was discussed and shown to improve the photo-generated current. The IBC-SHJ solar cells were fabricated using both the front surface passivation approaches and a 15% cell efficiency was achieved on 150µm thick FZ c-Si wafer without surface texturing and optical optimization.