Steven Yun Ji

Bit-pattern sensitivity analysis and optimal on-die-termination for high-speed memory bus design

System IO power and performance are critical computer platform design parameters. IO power forms a significant portion of the overall power while its performance is often the bottleneck in achieving overall performance specification. This paper experimentally demonstrates, for the first time, optimal on-die-termination (ODT) schemes for DDR3-800MT/s and DDR3-1067 MT/s, revealed by thorough bit-pattern sensitivity analysis. Optimal ODT at IO receiver pads is proposed as a new critical design knob to achieve optimized power-performance trade-offs, dramatically improving signal integrity and power consumption. The thorough bit-pattern sensitivity analysis was found to be 100% more accurate than traditional approach. Up to 50% reduction in power consumption, 100%) increase in timing margin, and 100%> increase in voltage margin were demonstrated as the impact of the choice of ODT. It is also promised to become more important in the future at higher data rate.

Study of package EMI reduction for GHz microprocessors

As the operating frequency of the processor approaches 1 GHz and beyond, the package dimensions are no longer small when compared to the wavelength. In order to reduce the emissions from the package, it is necessary to include certain package design features. Three different package designs are investigated to study their relative efficiency in suppressing the emissions. The first package design uses ground patches to reduce cross talk. This scheme was observed to be increasing emissions beyond 1.5 GHz. The second package design utilized stitching vias to suppress the radiation. This scheme was observed to be ineffective in suppressing emissions due to many existing power and ground vias within the area under the die. The existing vias with checkerboard for low loop inductance design results excellent EMI reduction up to 20 GHz. The third design uses the retreated power plane to reduce the emission, and it shows good performance.

An empirical study of performance and power scaling of low voltage DDR3

Memory power consumption has become a main driving force of new memory technologies. Low voltage DDR3 (DDR3L) has emerged to provide optimal solution for performance and power for certain market segments. With empirical data, this paper demonstrates the scaling of DDR3L signal integrity performance and power consumption at full system level. The signal integrity performance is degraded by 10∼20% in terms of voltage and timing margin with strong DRAM vendor sensitivity. The DRAM power consumption is reduced by ∼20%. The impact to mobile notebook average and self-refresh power is also examined.

Cost competitive PI-SI co-design for DDR interfaces

The total DDR on-die AC power delivery noise can be decomposed into high pass filtered (HPF) Vppa and low pass filtered (LPF) Vppb. PI-SI co-simulation reveals that Vppa impacts timing (eye width) and Vppb impacts signal voltage amplitude (eye height), and they need to be budgeted in different manner. Consequently the Power Delivery Network (PDN) is optimized with significant Cpkg and Cdie reduction for a small form factor while maintaining the reliable SI performance, which is demonstrated with a DDR interface and correlated with lab measured data on a particular SoC platform.

Signaling margin oriented LPDDR PDN design with SIPI synthesis methodology

Signal margin oriented SIPI analytical synthesis methodology is developed for PI design with concurrence of SI design based upon PDA for LPDDR interfaces. The SIPI analytical synthesis results are well correlated with empirical Spice simulation results with circuit netlist for current and voltage waveforms, and also with lab measurements for singling margins on a particular platform with LPDDR3. Consequently, global cost competitive PDNs and optimal SI channel are achievable simultaneously with SIPI synthesis methodology for all LPDDR technologies with increasing data rate.

Analysis and system optimization of high performance clocking for modern mobile platforms

Modern mobile platforms contain mainly active components in a small area with stringent power and cost targets. An integrated clock is needed for PLLs, component internal functions as well as transferring data among them. Due to the small mobile form factors, the noise coupling from power/ground and signals to the integrated clock circuitry becomes more evident impacting clock performance significantly. A method of signal and power integrity analysis and system optimization is proposed to design clocks in System-on-Chip (SoC), package and platform of mobile products such as wearables, phones and tablets. The measured results from high volume mobile systems show 30% clock jitter reduction from generation to generation using the frequency domain analysis and system optimization.

A methodology to characterize USB3 IO link signal margin variation in high volume manufacturing

High-speed IO performance verification is challenging due to system variations across high volume manufacturing. This paper presents a methodology to quantify variations caused by several IO subcomponents including transmitter, receiver, channel, test repeatability and concurrency effects. A tablet USB3 design was used as an example to illustrate the method.

A Practical Method to Characterize Interconnect in a Fully Loaded System, and its Application to DDR3 Channel

In this paper we formulate and apply a practical method to characterize DDR3 interconnect in a fully loaded system where two-port measurements are not feasible, in most cases due to design topology. To overcome these limitations, we present a technique that allows two-port s-parameters extraction from three VNA or TDR one-port measurements. The method is shown to be highly accurate up to 20 GHz, thus suitable for multi-gigabit signaling system. Additionally, this paper presents time-domain differentiation technique to obtain precise frequency response of a measured TDR waveform, both magnitude and phase. The reflection coefficient can then be used to obtain two-port s-parameters from three TDR measurements. Measurement-simulation correlation of memory channel s-parameters was described and worst-case eye diagrams were computed. This paper is presented in the context of ever-growing requirement for memory channel bandwidth.

Time and frequency domain memory channel characterization and correlation methodology

First, this paper discusses a robust and efficient de- embedding technique that can be used for TDR-PNA- simulation correlation in time or frequency domain. Employing the de-embedding technique, TDR-PNA was shown to correlate very well with 2 mV resolution in time- domain, when TDR repeatability is 2 mV. Next, a systematic analysis of memory channel TDR-simulation correlation was detailed. Time domain correlation served as an efficient and straightforward way of capturing impedance discontinuities and crosstalk level. Finally, some design, modeling, and measurement guidelines for platform memory interconnect development were recommended.