Stuart Kleinfelder

THE SILICON VERTEX DETECTOR OF THE COLLIDER DETECTOR AT FERMILAB

Abstract A silicon microstrip vertex detector has been constructed and installed in the Collider Detector at Fermilab. The device has been designed to operate at a hadron collider. It began collecting data in May of 1992 and has functioned within specification. Technical details are presented on all aspects of the system and its performance.

Novel integrated CMOS sensor circuits

Three novel integrated CMOS active pixel sensor circuits for vertex detector applications have been designed with the goal of increased signal-to-noise ratio and speed. First, a large-area native epitaxial silicon photogate sensor was designed to increase the charge collected per hit pixel and to reduce charge diffusion to neighboring pixels. High charge to voltage conversion is maintained by subsequent charge transfer to a low capacitance readout node. Second, a per-pixel correlated double sampling kT/C reset noise reduction circuit was tested. It requires only one read, as compared to two for typical double sampling in active pixel sensors, and no off-pixel storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5 to a measured 15.6 e/sup -/, rms. Finally, a column-level active reset technique was designed that suppresses kT/C reset noise. It reduced noise by up to a factor of 7.6, to an estimated 8.3 input-referred electrons, rms. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21. This may reduce pixel-by-pixel pedestal differences enough to permit sparse data scan without per-pixel offset corrections.

Gigahertz waveform sampling and digitization circuit design and implementation

A series of multichannel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel 10-bit digitization have been designed, tested, and fabricated in large quantities. The current CMOS circuit uses four arrays of 128 fast switched capacitors per channel to record four parallel analog transient inputs. High-speed sample clock generation is provided by an analogically adjustable asynchronous active delay line that uses look-ahead to generate 128 multi-GHz four-way interleaved clocks without the need for external high-speed clocking. After transient capture, each channel is fed into 128 parallel 10-bit analog to digital converters for fast, channel-parallel digitization, followed by digital readout. The fast triggering and waveform capture, channel-parallel digitization and convenient word-parallel digital readout results in a responsive and low dead-time system. Acquisition sample rates range from /spl sim/50 kHz to /spl sim/3 GHz. Analog input bandwidth was measured to be /spl sim/350 MHz. Temporal noise is typically equivalent to /spl sim/1 mV root mean square (rms) for a signal-to-noise ratio of /spl sim/2500:1 rms. Fixed-pattern spatial noise, after on-chip digitization, is equivalent to /spl sim/5 mV rms. Current design directions are intended improve on this technology with sample rates in excess of 10 GHz and an analog bandwidth exceeding 1 GHz.

A first search for cosmogenic neutrinos with the ARIANNA Hexagonal Radio Array

The ARIANNA experiment seeks to observe the diffuse flux of neutrinos in the 10 − 10 GeV energy range using a grid of radio detectors at the surface of the Ross Ice Shelf of Antarctica. The detector measures the coherent Cherenkov radiation produced at radio frequencies, from about 100 MHz to 1 GHz, by charged particle showers generated by neutrino interactions in the ice. The ARIANNA Hexagonal Radio Array (HRA) is being constructed as a prototype for the full array. During the 2013-14 austral summer, three HRA stations collected radio data which was wirelessly transmitted off site in nearly real-time. The performance of these stations is described and a simple analysis to search for neutrino signals is presented. The analysis employs a set of three cuts that reject background triggers while preserving 90% of simulated cosmogenic neutrino triggers. No neutrino candidates are found in the data and a model-independent 90% confidence level Neyman upper limit is placed on the all flavor ν + ν̄ flux in a sliding decade-wide energy bin. The limit reaches a minimum of 1.9×10−23 GeV−1 cm−2 s−1 sr−1 in the 10 − 10 GeV energy bin. Simulations of the performance of the full detector are also described. The sensitivity of the full ARIANNA experiment is presented and compared with current neutrino flux models.

First use of a high-sensitivity active pixel sensor array as a detector for electron microscopy

There is an urgent need to replace film and CCD cameras as recording instruments for transmission electron microscopy (TEM). Film is too cumbersome to process and CCD cameras have low resolution, marginal to poor signal-to-noise ratio for single electron detection and high spatial distortion. To find a replacement device, we have tested a high sensitivity active pixel sensor (APS) array currently being developed for nuclear physics. The tests were done at 120 keV in a JEOL 1200 electron microscope. At this energy, each electron produced on average a signal-tonoise ratio about 20/1. The spatial resolution was also excellent with the full width at half maximum (FWHM) about 20 microns. Since it is very radiation tolerant and has almost no spatial distortion, the above tests showed that a high sensitivity CMOS APS array holds great promise as a direct detection device for electron microscopy.

Integrated x-ray and charged particle active pixel CMOS sensor arrays using an epitaxial silicon-sensitive region

Integrated CMOS Active Pixel Sensor (APS) arrays have been fabricated and tested using X-ray and electron sources. The 128 by 128 pixel arrays, designed in a standard 0.25 micron process, use a ~10 micron epitaxial silicon layer as a deep detection region. The epitaxial layer has a much greater thickness than the surface features used by standard CMOS APS, leading to stronger signals and potentially better signal-to-noise ratio (SNR). On the other hand, minority carriers confined within the epitaxial region may diffuse to neighboring pixels, blur images and reduce peak signal intensity. But for low-rate, sparse-event images, centroid analysis of this diffusion may be used to increase position resolution. Careful trade-offs involving pixel size and sense-node area verses capacitance must be made to optimize overall performance. The prototype sensor arrays, therefore, include a range of different pixel designs, including different APS circuits and a range of different epitaxial layer contact structures. The fabricated arrays were tested with 1.5 GeV electrons and Fe-55 X-ray sources, yielding a measured noise of 13 electrons RMS and an SNR for single Fe-55 X-rays of greater than 38.

CMOS active pixel sensor achieving 90 dB dynamic range with column-level active reset

A CMOS active pixel sensor array using column-level active reset has been fabricated and tested. Column-level active reset requires one additional transistor per pixel, bringing the total to 4, and a per-column op-amp. The added transistor per pixel controls the gate of the reset transistor. There are two important feedback mechanisms in active reset. The first is the amplification by the Miller effect of the effective capacitance on the photodiode during reset, hence reducing kT/C noise. The second is the control of the resetting current via modulation of the transconductance of the reset switch. The level of noise reduction is comparable to, or may exceed, what true correlated double sampling can achieve. Readout noise of 44 microvolts and a dynamic range of 90 dB (15 bits), rms, has been measured. Room temperature noise as low as 5.1 electrons, rms, referred back to the photodiode node, has been measured on small photodiode pixels (5.8 fF capacitance). This compares to 38.3 electrons when measured with a standard “hard” reset, for a factor of 7.6 improvement. Row and column fixed pattern noise were also improved by up to a factor of 21, going from 1% for both to 0.048% and 0.27%, respectively.

A multi-GHz, multi-channel transient waveform digitization integrated circuit

A series of multi-channel transient waveform digitization integrated circuits with up to 5 GHz sample rates and parallel 10-bit digitization has been designed, tested, and fabricated in large quantities. The current CMOS circuit uses four arrays of 128 fast switched capacitors per channel to record four parallel analog transient inputs. Triggering and clocking is provided by an analogically-adjustable asynchronous active delay line that uses look-ahead to generate 128 multi-GHz 4-way interleaved clocks without the need for external high-speed clocking. After transient capture, each channel is fed into 128 parallel 10-bit analog to digital converters for fast, channel-parallel digitization, followed by digital readout. The fast triggering and waveform capture, channel-parallel digitization and convenient word-parallel digital readout results in a responsive and low dead-time system. Acquisition sample rates range from /spl sim/50 kHz to /spl sim/3 GHz. Analog input bandwidth was measured to be /spl sim/350 MHz. Temporal noise is typically equivalent to /spl sim/1 mV RMS, for a signal to noise ratio of /spl sim/2,500:1, RMS. Fixed-pattern spatial noise, after on-chip digitization, is equivalent to /spl sim/5 mV, RMS. Current efforts to improve this technology will yield larger array sizes, sample rates in excess of 10 GHz, analog bandwidth exceeding I GHz, higher conversion rates, lower dead-time, and enhanced flexibility.

High-Speed, High Dynamic-Range Optical Sensor Arrays

A monolithic solid-state linear sensor array has been designed and fabricated in a 0.35 mum , 3.3 V, thin-oxide digital CMOS process. The sensor arrays are targetted at such instruments and applications as digital streak cameras, 2-D cameras for proton radiography, and fiber-optic array readout. The prototype consists of a 1-D linear array of 150 integrated photodiodes, followed by fast analog buffers and on-chip, 150-deep analog frame storage. Frame storage consists of 150 analog sample circuits per pixel, with each sample circuit including an n-channel sample switch, a 0.1 pF double-polysilicon sample capacitor, a reset switch to clear the capacitor, and a multiplexed source-follower readout buffer. Sampling speeds of 400 M-frames/s have been achieved using electrical input signals, and 100 MHz with optical input signals, both with a dynamic range of ~ 11.5 bits, rms. Circuit design details are presented, along with the results of electrical measurements and optical experiments with fast pulsed laser light sources at several wavelengths. A set of next-generation concept designs are also presented that aims to include PLL-based clock multiplication for 1 GHz continuous sampling, plus a new real-time trigger circuit technique that examines windowed regions of stored samples to form a sophisticated trigger decision.

Novel integrated CMOS pixel structures for vertex detectors

Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e/sup -/. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e/sup -/ input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.