Subindu Kumar

Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC–DC buck converter

Summary This paper presents a semi-automated word-length optimization framework to reduce field-programmable gate array (FPGA) resource utilization for FPGA-based pre-silicon test emulation of analog and mixed signal circuits while achieving the desired accuracy and overcoming long optimization time. Although high-level behavioral models exist for modeling analog and mixed signal circuits, these comprise many complex differential equations which cannot be realized implicitly using Boolean logic (which is the basic functional block of an FPGA) on an FPGA. So, a more convenient way is explored to map analog circuits into digital domain by converting them into fixed-point architectures because of its advantage of manipulating data with lower word-length. To address the loss of accuracy due to finite word-length effects and limited reconfigurable resources, word-lengths are optimized under the constraint of given performance metrics. The proposed technique built in MATLAB/Simulink environment with Xilinx System Generator support is illustrated with the help of a case study of a peak-current-mode-controlled buck-type switching converter implemented on Xilinx Virtex™-5 FPGA. To illustrate the applicability of this environment for pre-silicon test development, well-accepted fault models are emulated with the help of non-ideal model of a buck converter. The emulation results are seen to be close to that of a post-fabricated power converter in the presence of faults. Experimental results show that FPGA resource utilization can be reduced significantly while achieving the desired performance accuracy under the constraint of multiple error metrics. Copyright

SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis.

This paper presents a new approach for simulating single analog faults in linear analog circuits modeled in MATLAB/Simulink environment. The proposed approach consists of namely, modeling fault free, and faulty analog circuits in MATLAB/Simulink environment using signal flow graph, simulating both models applying an input test stimulus and identifying the presence of faults by comparing the maximum error voltage measured at the output with a predefined threshold. The parametric faults are modeled in terms of component tolerances. Apart from this, catastrophic faults are also considered in terms of short and open faults. The proposed approach initially identifies the type of fault to be simulated. Based on fault type, it builds the signal flow graph (SFG) of the faulty circuit. We have also shown that parametric faults are sensitive to frequency of the input test sinusoid. Our proposed approach exploits ‘PSpice® Advanced Sensitivity Analysis’ which identifies less sensitive parametric faults at a given frequency of input sinusoid. The effectiveness of the proposed method is verified by fault modeling and fault simulation of a biquadratic and leapfrog filter circuit. The proposed fault simulation method provides a speedup over the traditional circuit simulator like PSPICE.