Subramaniam Ganesan

A microprocessor-based dual slope phase meter

A dual-slope phase meter has been designed and tested to investigate its limitations. The design does not require a time standard; it offers good resolution, relative simplicity, low sensitivity to changes of internal circuit parameters, and microprocessor compatibility. The idea is based on a single-slope approach demonstrated by W.T. Davis (1986), but several disadvantages of the system have been eliminated. The main problem with the system, relating to the error due to the finite time of sampling, is discussed. >

Bus arbitration in an embedded processor-shared multiprocessor system

Bus arbitration scheme for a partially processor shared-memory system embedded in a general reconfigurable R(n,m) system is presented where n is the number of global processors, and m is the number of global memory modules. The effective cost for the arbitration and crosspoint switch control is absorbed within the hardware implementation of a SIMD array processor which can be used as a crosspoint switch controller. This embedded system shows an improvement of bandwidth over conventional group based bus systems.<<ETX>>

Hough Transform For Vehicle Identification

This paper describes a vision based vehicle identification algorithm. This algorithm has been developed using image processing and pattern recognition techniques. The paper describes the role of the image processing techniques in this algorithm, specifically, the application of the Hough Transform in this scheme.

An algorithm driven architecture for a lossless image compression scheme based on multiplicative autoregressive models

We propose an algorithm driven architecture design for a lossless image scheme. The proposed architecture uses the spatial parallelism present in the block-based compression algorithm. Various schemes of implementation of the architecture are discussed and compared with the sequential implementation of the compression algorithm.

Reconfigurable shared and dedicated-bus multiprocessor for parallel computing

Abstract A reconfigurable multiprocessor architecture embedding a shared-bus connected system and an SIMD dedicated-bus system is proposed in this paper. The shared-bus system uses a reduced number of buses. The reconfiguration is achieved through programmable internal switches and crosspoint switches. The aim in developing this reconfigurable architecture is to provide flexibility in choosing various architectures based on the structure of parallel algorithms and parallel computation. We analyze the bandwidth of the shared-bus system and compare the results with a general multiple-bus architecture.

A dual-DSP microprocessor system for real-time digital correlation

Abstract The design of a dual TMS320C25 DSP microprocessor system with dual-port common memory and its application for real-time correlation are explained. System design details, brief explanations for design decisions and timing analysis, theory of digital correlation, a software flowchart and a description of hardware-software debugging using the XDS 320 simulator and a software simulator are presented.

A hardware cache coherency scheme for multiprocessors

In this paper, we discuss a hardware cache coherency scheme for shared memory multiprocessors. The scheme consists of a cache coherency protocol and a hardware scheme for cache coherency. Use of the scheme allows one to split cache coherency operations between the participating processors. Protocol states and operations are discussed. A cache controller architecture is proposed for this protocol and its design details are discussed. Performance of the coherency scheme is also discussed.<<ETX>>

An SIMD multiple DSP microprocessor system for image processing

Abstract In this paper, we discuss a parallel processor design using eight DSP microprocessors (TMS320C25) and dual-port RAMs for image processing applications. The application of image processing algorithms on this architecture, hardware details, performance analysis, simulation of image processing algorithms and comparison with architectures reported in the literature are also discussed.

Datapath synthesis using genetic algorithm

Abstract The Application Specific Integrated Circuit (ASIC) synthesis is optimized using Genetic Algorithm (GA) for many types of ASICs including microprocessors, datapaths and ASIC floor plan layout. The implementation methodology of GA is developed after implementing several GA-based Datapath synthesis algorithms. The methodology is found to be very effective in Datapath synthesis problems. Global optimization of scheduling, allocation and datapath synthesis of HAL (Lee J, Hsu Y, Lin Y. A new integer linear programming formulation for the scheduling program in data path synthesis. In: Proceedings of the International Conference on Computer-Aided Design, 1989;20–23) circuit using knowledge based GA are described here. The results of the above optimization are validated using conventional optimization methods.

A Re-Configurable Reduced-Bus Multiprocessor Interconnection Network

Multiple-bus multiprocessor interconnection networks are still considered as a cost effective and easily expandable processor-memory interconnection. But, a fully connected multiple bus network requires all busses to be connected to each processor and memory module thus increasing the physical connection and the bus load on each memo y. Reduced-bus connections with different connection topology such as rhombus, trapezoidal etc., were presented in [l]. In this paper a general single network topology has been presented that can be reconfigured to any one of the reduced-bus connection schemes. The re-configurability is achieved through the arbitration of combinations of simple link switches in a ring structure. The motive behind developing this reconfigurable structure is to offer a flexibility in matching the reduced-bus connection schemes to structure of parallel algorithms. The paper presents a mapping scheme to arbitrate the link switches for various connection pattems. Also, a comparison of effective memoy bandwidth of each connection scheme is shown. Expandability of the system to larger sizes are addressed.