Sudakshina Kundu

Simulation to Study the Effect of Oxide Thickness and High-

The effect of variation of oxide thickness on the drain-induced barrier lowering, simulation parameter of a conventional MOSFET has been studied, first theoretically by proposing a new numerical method and then verifying by simulating with Sentaurus TCAD Toolkit. Since SiO2 has its limitations at very low oxide thicknesses, improvement in the performance of the MOS by using high- K dielectric material for gate-channel isolation has also been studied.

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In this paper we furnish a novel approach of design automation and optimization of CMOS analog integrated circuits. This method offers an effective amalgamation between the principles of orthogonal-convex optimization and the all-inversion region MOS transistor model. We have observed that the constituting equations of the all-inversion region MOS model share great resemblance with the standard representation of orthogonal-convex functions. Therefore, these design equations, emerging from various device and circuit specifications can be modelled as the constraints of an orthogonal-convex optimization problem and can be evaluated automatically to ensure a globally optimal solution over a range of design scenarios. Additionally, there is a provision for design feasibility analysis with this semi-empirical approach.

Dielectric on Drain-Induced Barrier Lowering in N-type MOSFET

In this paper we furnish a novel approach of design automation and power optimization of CMOS analog integrated circuits. This method offers an effective amalgamation between the principles of orthogonal-convex optimization and the all-inversion region MOS transistor model. The design equations, emerging from various device and circuit specifications can be modeled as the constraints of an orthogonal-convex optimization problem and can be evaluated automatically to ensure a globally optimal solution over a range of design scenarios.

Constrained Optimization of CMOS Analog Circuits via All-Inversion Region MOS Model

In this work, the Drain Induced Barrier Lowering is studied as the function of oxide thickness and substrate doping. The effects are verified simulating with TCAD Sentaurus toolkit. High-K dielectric material is used in place of SiO2. Also investigation of the effect of change in substrate doping on Drain Induced Barrier Lowering is studied.

Constrained low-power CMOS analog circuit design via all-inversion region MOS model

Multi Threshold CMOS (MTCMOS) circuit can be used to overcome the trade-off between speed and standby leakage current inherent in single threshold CMOS circuit. The simplest form is the dual threshold CMOS (DTCMOS), in which two threshold voltages are used in the same logic circuit. As a result, the standby power can be greatly reduced by this approach which is a key factor for battery operated devices. This paper proposed a model for analytical calculation of standby leakage current for MTCMOS Inverter circuit in 90nm technology. We have used BSIM device model which is a widely used industrial model for standby leakage current modelling of MTCMOS Inverter circuit.

Simulation to study the effect of variation of oxide thickness and substrate doping on DIBL in MOSFET

Polysilicon gates have replaced the metal gates in CMOS technology. If the doping is not high enough in polysilicon then the flatband voltage should be corrected. Polysilicon gates are also depleted with the application of gate voltage. The dependence of MOSFET current (Ids) on polysilicon gate concentration is studied using the results simulated by Sentaurus TCAD tool in case of N channel MOSFETs. With the decrease in polysilicon gate doping concentration (Nd), the drain current is more degraded. A theory is developed, in order to explain the simulation results that take into consideration the correction in flatband voltage and the voltage drop due to polysilicon depletion. From the analysis of simulated and theoretical curves, an inversion region is suspected to occur at the polysilicon gate for low doping concentration at high gate voltage.