Sudeep Bhoja

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS

High-speed signaling using NRZ has approached speeds above 50Gb/s where it is extremely difficult to maintain power efficiency and performance over a wide variety of channels and applications. PAM-4 is emerging as one way to increase throughput in such band-limited channels. Higher modulation formats help to address cost in optical systems by packing more bits/wavelength [1]. Strong momentum in standards to adopt PAM-4 reflects these significant trends in the industry. At the same time, migrating transceiver designs to current technology nodes have narrowed the power gap between traditional Analog and ADC-DSP-DAC-based systems for high-speed applications. These factors make ADC-based receivers a highly desirable choice, as is also the trend in wireless communications.

Feasibility of unretimed 100 GbE based on 4×25.78 GBd

We have demonstrated the feasibility of unretimed 100 GbE based on 4×25.78 GBd signaling, using a 40 nm CMOS SerDes interfaced to a 100 mm host PCB channel that includes a z-pluggable connector connected to a 100Gbase-LR4 ROSA.