Sug Hun Hong

Influence of the oxygen concentration of atomic-layer-deposited HfO2 films on the dielectric property and interface trap density

The influence of the ozone concentration (160–370g∕m3) during atomic layer deposition of HfO2-gate dielectrics on the dielectric performance of the films grown on Si was studied. Although ozone was effective in reducing the impurity concentration in the film compared to H2O, the higher concentration slightly deteriorated the dielectric performance. More importantly, the degradation in the interface trap property with increasing post-annealing temperature became more serious as the ozone concentration increased. Investigation of the interface states using x-ray photoelectron spectroscopy revealed that the excessive oxygen incorporated during the film growth made the interfacial sub-oxide species (SiO, Si2O3, and silicate) and SiO2 coordinate more with oxygen. This increased the interface trap density and degraded the interface properties.

Influence of the oxygen concentration of atomic-layer-deposited HfO2 gate dielectric films on the electron mobility of polycrystalline-Si gate transistors

The influence of the ozone concentration (150–370g∕m3) during the atomic layer deposition of HfO2 gate dielectrics on the dielectric performance of the films and the device performance of metal-oxide-semiconductor field effect transistor (MOSFET) grown on Si was studied. The use of a lower ozone concentration (150g∕m3) produced a HfO2 film with a stoichiometric oxygen concentration, whereas a higher ozone concentration (390g∕m3) produced an oxygen excess HfO2 film. An almost identical Dit to that of the SiO2 gate dielectric film was obtained from the stoichiometric HfO2, whereas the oxygen excess HfO2 gate dielectric produced a much higher Dit with the polycrystalline-Si electrode. The investigation of the interface states using x-ray photoelectron spectroscopy revealed that the excessive oxygen incorporated during the film growth made the interfacial reaction and oxidation serious. This increased the interface trap density and degraded the interface properties. Accordingly, an electron effective mobility...

Improvement of the current-voltage characteristics of a tunneling dielectric by adopting a Si3N4∕SiO2∕Si3N4 multilayer for flash memory application

Superior characteristics of an atomic-layer-deposited (ALD) Si3N4 layer and Si3N4∕SiO2∕Si3N4 stacked layers as a tunneling gate dielectric for nonvolatile flash memory application are reported. Compared to a single layer of SiO2 electric field-sensitive characteristics were obtained by barrier profile engineering with a stacked layer; a lower leakage current at a low field and a higher leakage current at a high field. The stacked dielectric layer showed Fowler–Nordheim tunneling. However, the interfacial potential barrier profile was somewhat smoothed by chemical interaction between the individual layers. The interfacial trap density of this dielectric with an ALD Si3N4 bottom layer was as low as 4×10−10∕cm2eV near the mid-gap energy state, but the reoxidation process degraded the interface quality. The degradation mechanism was studied.

Voltage-induced degradation in self-aligned polycrystalline silicon gate n-type field-effect transistors with HfO2 gate dielectrics

The voltage-induced degradation in the threshold voltage of field-effect transistors using atomic layer deposited HfO2-gate dielectrics was studied. Si channel surfaces of some samples were in situ pretreated using O3 flow before HfO2 deposition, which formed a very thin SiO2 interfacial layer. This avoided a shift of the threshold voltage up to a stress time of 1000s under inversion condition at +3V gate voltage. The transistors without O3 pretreatment showed a serious change in the threshold voltage by electron trapping. A leakage current measurement under inversion condition showed that the leakage current was not the major factor that controlled the degradation. Instead, the interfacial traps resulting from the Si suboxide formation for the cases without O3 pretreatment appeared to constitute the major reason for the degradation.

Improvement of the current-voltage characteristics of a tunneling dielectric by barrier engineering by adopting an atomic-layer-deposited SiN layer for flash memory applications

In this paper new and superior characteristics of an atomic layer deposited (ALD) SiN layer and SiN/SiO/sub 2//SiN multi layers as gate dielectric for flash memory application are reported. Field-sensitive characteristics compared to SiO/sub 2/ were obtained by barrier profile engineering with a SiN/SiO/sub 2//SiN stack; a lower leakage current at a low field and a higher leakage current at a high field. The stacked dielectric layer showed F-N tunneling. However, the interfacial potential barrier profile was somewhat smoothed by chemical interaction between the individual layers. The interfacial trap density of this dielectric with an ALD SiN bottom layer was as low as 4/spl times/10/sup -10//cm/sup 2/eV near the mid-gap energy state, but the re-oxidation process degraded the interface quality. The degradation mechanism was studied using electrical analysis, XPS, and TEM.

Dopant Penetration Behavior of B-Doped P + Polycrystalline- Si0.73Ge0.27 ∕ Al2O3 or AlN – Al2O3 ∕ n-Si Metal Insulator Semiconductor Capacitors

B-doped p + polycrystalline-silicon (poly-Si) or silicon germanium (poly-Si 0.73 Ge 0.27 ) gate/Al 2 O 3 or top nitrogen incorporated Al 2 O 3 (N-Al 2 O 3 )/n-type Si(100) metal insulator semiconductor capacitors were fabricated using atomic layer deposition for the Al 2 O 3 or AlN/Al 2 O 3 layer to investigate B penetration and device reliability. The adoption of a poly-Si 0.73 Ge 0.27 electrode greatly reduced the B penetration into the substrate through the Al 2 O 3 layer and enhanced the activation of the implanted dopant compared to the poly-Si electrode under a given activation annealing condition. The acquired work function engineering by the poly-Si 0.73 Ge 0.27 electrode also reduced the threshold voltage of the device. Deposition of a thin AlN layer on top of the Al 2 O 3 layer further reduced the B diffusion into the dielectric which greatly enhanced the dielectric reliability. The poly-Si 0.73 Ge 0.27 (N-Al 2 O 3 )/n-type Si capacitors showed the smallest leakage current density of 3.0 X 10 -7 A/cm 2 at 1 V and a large charge-to-breakdown value of 8.5 C/cm 2 .

ELECTRICAL AND STRUCTURAL PROPERTIES OF High-k HfO2 on Si1-x Gex SUBSTRATES

The changes in the electrical and physical properties of HfO2 films grown using atomic layer deposition (ALD) on Si1-XGeX (x=0.1, 0.2, 0.3) substrates after post-annealing have been studied. The migration of Ge plays a key role in reducing the capacitance equivalent thickness (CET) whilst keeping the leakage current density constant after post-annealing. The Ge atoms which have already diffused into the HfO2 upper layer during deposition are drawn back to interfacial layer. Although the thickness of interfacial layer increases, the thickness shrinkage of HfO2 upper layer and increased permittivity of both layers achieves a reduction of the capacitance equivalent thickness.