Suganth Paul

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations

The realization of functions such as log() and antilog() in hardware is of considerable relevance, due to their importance in several computing applications. In this paper, we present an approach to compute log() and antilog() in hardware. Our approach is based on a table lookup, followed by an interpolation step. The interpolation step is implemented in combinational logic, in a field-programmable gate array (FPGA), resulting in an area-efficient, fast design. The novelty of our approach lies in the fact that we perform interpolation efficiently, without the need to perform multiplication or division, and our method performs both the log() and antilog() operation using the same hardware architecture. We compare our work with existing methods, and show that our approach results in significantly lower memory resource utilization, for the same approximation errors. Also our method scales very well with an increase in the required accuracy, compared to existing techniques.

FPGA-based hardware acceleration for Boolean satisfiability

We present an FPGA-based hardware solution to the Boolean satisfiability (SAT) problem, with the main goals of scalability and speedup. In our approach the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. The experimental results and their analysis, along with the performance models are discussed. We show that an order of magnitude improvement in runtime can be obtained over MiniSAT (the best-in-class software based approach) by using a Virtex-4 (XC4VFX140) FPGA device. The resulting system can handle instances with as many as 10K variables and 280K clauses.

Minimizing and Exploiting Leakage in VLSI Design

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.

Design and implementation of a sub-threshold BFSK transmitter

Power Consumption in VLSI circuits is currently a major issue in the semiconductor industry. Power is a first order design constraint in many applications. However, a growing class of applications need extreme low power but do not need high speed. Sub-threshold circuit design can be used for these applications. Unfortunately, sub-threshold circuits exhibit an exponential sensitivity to process, voltage and temperature (PVT) variations. In this paper we implement and test a robust subthreshold design flow which uses circuit level PVT compensation to stabilize circuit performance. We design and fabricate a subthreshold BFSK transmitter chip. The transmitter is specified to transmit baseband signals up to a data rate of 32kbps. Experiments using the fabricated die, verify the functionality of the design show that the sub-threshold circuit consumes 19.4× lower power than the traditional standard cell based implementation on the same die.

Computing Leakage Current Distributions

With leakage power increasing as a fraction of the total power of a design, due to the current design trends, it is arguably important to find the leakage for all input vectors. This is useful when comparing candidate implementations of a design with the same minimum leakage values. An implementation that has a leakage histogram with larger number of input vectors contributing to lower leakage values would be preferred over other implementations. This would not only minimize the leakage during the regular operation of the circuit, but also ease the task of finding a vector that results in minimum leakage state.

Part II: Conclusions and Future Directions

While the first part of this book discussed leakage reduction techniques, the second part focused on leakage exploitation. In Chap. 9 we first presented data from some exploratory studies that revealed the opportunity that sub-threshold circuit design offers. The main advantages of sub-threshold circuits are as follows: ● Low power consumption and heat dissipation ● Smaller delays with increasing temperature ● High power-delay product (PDP)

Design of the Chip

This chapter presents the design of a test application that will utilize the circuit design methodologies described in Part II of this book. Sect. 14.2 discusses the criteria used to choose a test application and also an overviewof what basic building blocks are required for such an application. It also defines the design constraints that are to be taken into accountwhile designing a sub-threshold circuit. The architecture of the whole system and the details of the sub-blocks of the system are covered in Sect. 14.3. This chapter also outlines some special considerations and redundant features and failure-safe features that are built into the chip. The design of the chip is targeted for the TSMC [2] 0.25_m process, which is a triple well CMOS process.

Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities

The control of leakage power consumption is a growing design challenge for current and future CMOS circuits. A heuristic approach (referred to as MLVC) is to determine the input vector that minimizes leakage for a combinational design. This approach utilizes approximate signal probabilities of internal nodes to aid in finding a minimal leakage vector. We utilize a probabilistic heuristic to select the next gate to be processed as well as to select the best state of the selected gate. A fast Boolean Satisfiability (SAT) solver is employed to ensure the consistency of the assignments that are made in this process. A variant of MLVC, referred to as MLVC-VAR, is also presented. MLVC-VAR includes the effect of random variations in leakage values due to process, voltage and temperature (PVT) variations. Including the effect of PVT variations for determining minimum leakage vector is crucial because leakage currents have an exponential dependence on power supply, threshold voltage and temperature. Experimental results indicate that our MLVC method has very low runtimes, with excellent accuracy compared to existing approaches. Further, the comparison of the mean and standard deviation of the circuit leakage values for MLVC with MLVC-VAR and an existing random vector generating approach proves the need for considering these variations while determining the minimum leakage vector. MLVC-VAR reports, on average, about 9.69% improvement over MLVC with similar runtimes and 5.98% improvement over the random vector generation approach with significantly lower runtimes.

Reclaiming the Sub-threshold Speed Penalty Through Micropipelining

Sub-threshold circuit design is an appealing means to dramatically reduce power consumption. However, sub-threshold designs suffer from the drawback of being significantly slower than traditional designs. To reduce the speed gap between sub-threshold and traditional designs, we propose a sub-threshold circuit design approach based on asynchronous micropipelining of a levelized network of PLAs.We describe the handshaking protocol, circuit design and logic synthesis issues in this context. Our preliminary results demonstrate that by using our approach, a design can be sped up by about 7×, with an area penalty of 47%. Further, our approach yields an energy improvement of about 4×, compared to a traditional network of PLA design. Our approach is quite general and can be applied to traditional circuits as well.

Optimum VDD for Minimum Energy

Operating circuits in the sub-threshold region or near the sub-threshold design can yield extremely low power circuits. However, for most applications that require ultra-low power, the lowest power solution is not necessarily the optimal solution from a minimum energy point of view. In this chapter, we describe a technique to find the energy optimum VDD value for a design, and show that for minimum energy consumption, the circuit may need to be operated at VDD values that are slightly higher than the NMOS threshold voltage value. We study this problem in the context of designing a circuit using a network of dynamic NOR-NOR PLAs.