Sugwon Hong

Design and Implementation of Multiagent-Based Distributed Restoration System in DAS

A distribution automation system (DAS) is a power automation system to operate a power distribution network efficiently through remote control and monitoring. The most important function of the DAS is the restoration of a stable power supply to the customer when a fault occurs. Since the DAS has a centralized structure, the restoration time of the DAS takes place in about 5 min. This is too long for a customer in the digital age, so a distributed restoration system, which can shorten the restoration time from 5 min to less than 1 min is proposed in this paper. The concept of a multiagent system (MAS) for a distributed control system is applied to the proposed system to enhance its operational reliability, but there is a belief that the MAS-based distributed operations system is just a future technology. So an application method is proposed in this paper for an MAS-based distributed restoration system without significant changes to the existing DAS. The proposed system was applied to an existing DAS and tested in the Gochang Power Testing Center. The test results showed that in the most complex case, the DAS restoration time was 48 s using a code-division multiple-access module and 10 s using an Ethernet communication module.

Security Protocols Against Cyber Attacks in the Distribution Automation System

As a communication technology plays an integral part in a power system, security issues become major concerns. This paper deals with the security problems in the distribution automation system (DAS) which has an inherent vulnerability to cyber attacks due to its high dependency on the communication and geographically widely spread terminal devices. We analyze the types of cyber threats in many applications of the distribution system and formulate security goals. Then we propose an efficient security protocol to achieve these goals. The protocol avoids complex computation of any encryption algorithm, considering resource-constraint network nodes. We also propose a secure key distribution protocol. Finally, we demonstrate the feasibility of the proposed security protocol by experiments.

Challenges and Direction toward Secure Communication in the SCADA System

In the past few years the security issues in the supervisory control and data acquisition (SCADA) system have been investigated, and many security mechanisms have been proposed from research communities. The international standard organizations also have published several standard documents for secured SCADA systems. In this paper we explain the technological challenges for the SCADA security and overview the approaches which address these challenges. Then we focus on the security protocol which has been proposed in the SCADA cyber security initiatives and implementation issues when the both security function and the communication function are implemented on the embedded system devices in future power grid including the SCADA network.

Distributed Restoration system applying Multi-Agent in distribution automation system

In this paper, as make up for the weak points of the centralized restoration in DAS, distributed restoration method applying multi-agent is proposed for increasing the efficiency and saving time of the restoration time of blackouts. Distribution restoration method is difficult to deal with a fault quickly because DAS manage, judge and order the states of distribution network after gathering all information from FRTUs when the fault occurs. If Feeder Remote Terminal Unit (FRTU) in distribution network performs restoration and separates minimized fault section itself by exchanging information using communication to each other, the efficiency and time of the restoration can be enhanced by much. In the case studies, this paper is proposed a distributed restoration method which can make up the weak points of the centralized restoration in DAS by converting FRTUs into multi-agents. The proposed method has been testified in Gochang power test field in Korea and the result in the restoration shows its performance.

Experiments for Embedded Protection Device for Secure SCADA Communication

Communication and security functions are considered to be the basic requirements to the electronic devices in the future power grid. Considering limited resources of the embedded field devices, developing the embedded protection devices poses a big challenge in building up the smart grid. This paper shows overhead for computing cryptographic algorithms at the device, and the performance degradation caused by incoming packet processing at embedded system devices. For this analysis we do some experiments on the operation which simulates message exchange in the SCADA system based on the IEC 61850. We also consider the security protocol for secure message exchange in the SCADA system. And then we consider the multi-core processor solution for implementing all required functions on the embedded devices as one possible approach.

Performance impact of resource conflicts on chip multi-processor servers

Chip Multi-Processors (CMPs) are becoming mainstream microprocessors for High Performance Computing and commercial business applications as well. Multiple CPU cores on CMPs allow multiple software threads executing on the same chip at the same time. Thus they promise to deliver higher capacity of computations performed per chip in a given time interval. However, resource sharing among the threads executing on the same chip can cause conflicts and lead to performance degradation. Thus, in order to obtain high performance and scalability on CMP servers, it is crucial to first understand the performance impact that the resource conflicts have on the target applications. In this paper, we evaluate the performance impact of the resource conflicts on an example high-end CMP server, Sun Fire E25K, using a standard OpenMP benchmark suite, SPEC OMPL.

High Throughput Parallel Implementation of Aho-Corasick Algorithm on a GPU

Pattern matching is an important operation in various applications such as computer and network security, bioinformatics, image processing, among many others. Aho-Corasick (AC) algorithm is a multiple patterns matching algorithm commonly used for such applications. In order to meet the highly demanding performance requirements imposed on these applications, achieving high performance for AC algorithm is crucial. In this paper, we present a high performance parallel implementation of AC algorithm on a Graphic Processing Unit (GPU) which efficiently utilizes the high degree of on-chip parallelism and the memory hierarchy of the GPU so that the aggregate performance (or throughput) of the GPU can be maximized. For this purpose our approach carefully places and caches the input text data and the reference pattern data used for pattern matching in the on-chip shared memories and the texture caches of the GPU. Furthermore, it efficiently schedules the off-chip global memory loads and the shared memory stores in order to minimize the overheads in loading the input data to the shared memories and also to minimize the shared memory bank conflicts. The proposed approach leads to a significant cut-down of the effective memory access latencies and leads to impressive performance improvements. Experimental results on Nvidia GeForce GTX 285 GPU show that our approach delivers up to 127Gbps throughput performance and up to 222-times speedup compared with a serial version running on 2.2Ghz Core2Duo Intel processor.

Memory Efficient Parallelization for Aho-Corasick Algorithm on a GPU

Pattern matching is a commonly used operation in many applications including image processing, computer and network security, bioinformatics, among many others. Aho-Corasick (AC) algorithm is one of the well-known pattern matching techniques and it is intensively used in computer and network security. In order to meet the real-time performance requirements imposed on these security applications, developing a high-speed parallelization technique is essential for the AC algorithm. In this paper, we present a new memory efficient parallelization technique which efficiently places and caches the input text data and the reference data in the on-chip shared memories and texture caches of the Graphic Processing Unit (GPU). Furthermore, the new approach efficiently schedules memory accesses in order to minimize the overhead in loading data to the on-chip shared memories. The approach cuts down the effective memory access latencies and leads to significant performance improvements. Experimental results on Nvidia GeForce 9500GT GPU shows up to 15-times speedup compared with a serial version on 2.2Ghz Core2Duo Intel processor, and 15Gbps throughput performance.

Evaluating Security Algorithms in the Substation Communication Architecture

Security becomes the major concern in a modernized electricity network. The IEC 61850 standard has been developed for substation automation, providing more enhancing communication functionalities. The standard defines several kinds of messages for data exchange between nodes in the substation. Among them, two critical messages have very stringent performance requirement for secure substation operation and protection. In this paper we design a security protocol for guaranteeing message authentication and integrity. In order to show whether the protocol can achieve the performance criteria imposed by the standard, we conduct some experiments on a desktop PC and an embedded device. Our study shows that the desktop PC is capable of satisfying performance criteria. However, the result shows that the embedded device has some limitation of handling incoming messages and processing cryptographic computation depending on the number of packets.

LSTAFF: system software for large block flash memory

Recently, flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristics, it requires a software layer called FTL (flash translation layer). We present a new FTL algorithm called LSTAFF (Large STAFF). LSTAFF is designed for large block flash memory. That is, LSTAFF is adjusted to flash memory with pages which are larger than operating system data sector sizes. We provide performance results based on our implementation of LSTAFF and previous FTL algorithms using a flash simulator.