Sujoy Sinha Roy

Pushing the limits of high-speed GF (2 m ) elliptic curve scalar multiplication on FPGAs

In this paper we present an FPGA implementation of a high-speed elliptic curve scalar multiplier for binary finite fields. High speeds are achieved by boosting the operating clock frequency while at the same time reducing the number of clock cycles required to do a scalar multiplication. To increase clock frequency, the design uses optimized implementations of the underlying field primitives and a mathematically analyzed pipeline design. To reduce clock cycles, a new scheduling scheme is presented that allows overlapped processing of scalar bits. The resulting scalar multiplier is the fastest reported implementation for generic curves over binary finite fields. Additionally, the optimized primitives leads to area requirements that is significantly lesser compared to other high-speed implementations. Detailed implementation results are furnished in order to support the claims.

Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed

This paper uses a theoretical model to approximate the delay of different characteristic two primitives used in an elliptic curve scalar multiplier architecture (ECSMA) implemented on k input lookup table (LUT)-based field-programmable gate arrays. Approximations are used to determine the delay of the critical paths in the ECSMA. This is then used to theoretically estimate the optimal number of pipeline stages and the ideal placement of each stage in the ECSMA. This paper illustrates suitable scheduling for performing point addition and doubling in a pipelined data path of the ECSMA. Finally, detailed analyses, supported with experimental results, are provided to design the fastest scalar multiplier over generic curves. Experimental results for GF(2163) show that, when the ECSMA is suitably pipelined, the scalar multiplication can be performed in only 9.5 μs on a Xilinx Virtex V. Notably the design has an area which is significantly smaller than other reported high-speed designs, which is due to the better LUT utilization of the underlying field primitives.

Revisiting the Itoh-Tsujii Inversion Algorithm for FPGA Platforms

The Itoh-Tsujii multiplicative inverse algorithm (ITA) forms an integral component of several cryptographic implementations such as elliptic curve cryptography. For binary fields generated by irreducible trinomials, this paper proposes a modified ITA algorithm for efficient implementations on field-programmable gate-array (FPGA) platforms. Efficiency is obtained by the fact that the adapted ITA algorithm uses FPGA resources better and requires shorter addition chains. Evidence is furnished and supported with experimental results to show that the proposed architecture outperforms reported results. The proposed method is also shown to be scalable with respect to field sizes.

A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms

Elliptic curve scalar multiplication is the central operation in elliptic curve cryptography. The paper presents a parallel architecture to accelerate scalar multiplications on Koblitz curves. The scalar multiplier architecture converts the scalar into τ-NAF representation and processes the zero digits of the scalar in parallel to point additions. Since the conversion from integer to τ-NAF is a time consuming operation, the proposed architecture uses recently developed double lazy reduction algorithm for conversion of scalar. The scalar multiplier processes two consecutive τ-NAF digits in every iteration. This facilitates parallel processing of large number of consecutive zero digits during a single point addition and practically no time is spent for processing the zero digits of the scalar. The proposed techniques are incorporated in a scalar multiplier and validated on Xilinx Virtex IV FPGA. Experimental results show that our architecture in F2163 has the best performance and has the computation time comparable with the fastest known implementation, which uses window based scalar multiplication algorithm.

Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs

Maximizing the performance of the Itoh-Tsujii finite field inversion algorithm (ITA) on FPGAs requires tuning of several design parameters. This is often time consuming and difficult. This paper presents a theoretical model for the ITA for any Galois field and fc-input LUT based FPGA (k > 3). Such a model would aid a hardware designer to select the ideal design parameters quickly. The model is experimentally validated with the NIST specified fields and with 4 and 6 LUT based FPGAs. Finally, it is demonstrated that the resultant designs of the Itoh-Tsujii Inversion algorithm is most optimized among contemporary works on LUT based FPGAs.

Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs

Among all finite field operations, finite field inversion is the most computationally intensive operation. Yet, it is an essential component of several public-key cryptographic algorithms such as elliptic curve cryptography. For hardware implementations over extended binary fields, the Itoh-Tsujii inversion algorithm (ITA) is the most efficient. In this paper we propose acceleration techniques for ITA on FPGA platforms. We first propose a generalization of the parallel ITA which uses exponentiation by 2^n and 2^n, where n>=1. Parallel ITA has several drawbacks which limit its speed. We propose a novel technique supported with theoretical analysis to overcome the drawbacks. The technique reduces the critical delay of the ITA architecture without increasing the clock cycle requirement. Experimental results are presented to show that the proposed technique outperforms reported results.

Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAs

The Itoh-Tsujii multiplicative inversion algorithm (ITA) is the most efficient finite field inversion algorithm for hardware based implementations over extended binary fields. In this paper we propose a novel technique to reduce the computation time of the ITA by saving clock cycles without increasing the delay and area significantly. In order to compare, we have designed the architecture for the ITA in the field GF(2193). The architecture uses a configuration of a cascaded quad-root block in parallel with a 297 circuit to compute the inverse in only .53 ¼secs on a Virtex E FPGA and .14 ¼secs on a Virtex V FPGA. Experimental results are presented to support that the architecture takes least computation time compared to other reported results.