Sukin Yoon

The Influence of the Data Signal on Transmission Characteristics of LCD Cells

In this paper, we report our preliminary study about the influence of data signal on the optical properties of LCD cell which is operated at vertical alignment (VA) mode. The VA cell employed in this study has a size of 88 × 264 μm2 with a cell gap of 4 μm. In order to analyze the optical crosstalk between the data signals, we employed finite element method (FEM) for calculating the LC director distributions and 2 × 2 extended Jones method for optical transmission. Our simulation revealed that the voltage discrepancy between data signal and pixel electrode voltage is the main cause for the reduction of brightness as well as the generation of flickers.

THREE-DIMENSIONAL NUMERICAL SIMULATION FOR UNDERSTANDING THE FRINGE-FIELD EFFECT ON THE DYNAMIC BEHAVIOR OF LIQUID CRYSTAL

A three-dimensional numerical study for understanding the fringe-field effect on the dynamic behavior of liquid crystal is presented. Our three-dimensional numerical simulator (TechWiz LCD) is based on the FEM (finite element method) formulation of Ericksen-Leslie equation, flow equation, and Laplace equation. Since our FEM solver has a fully unstructured mesh generator, it is possible to investigate the dynamic performance of any mode of LC cell with an arbitrarily shaped electrode structure including a chevron-type LC cell. In this paper, we report our preliminary result on the simulation of the dynamic behavior of the fringe-filed switching (FFS) mode LC cell that is designed for the fast response and wide viewing angle. The simulated dynamic response of the director distribution for the FFS-mode LC cell is also compared with experimental observations. The simulation reveals that most of the directors over the LC cell experience horizontal rotations despite the existence of both the vertical and the horizontal electric fields in the LC cell.

A mesh generation algorithm for complex geometry [semiconductor process modelling]

A mesh generation algorithm for a curved surface is proposed to investigate a complex structure on a semiconductor substrate. This algorithm relies on the advancing front method with scattered data interpolation through a NURBS (nonuniform rational B-spline) surface. This algorithm has been applied to a cell-based simulation and a level set simulation. The NURBS mesh according to our algorithm excellently represented the surface evolution of the topography.

Automatic Extraction of an Equivalent Circuit from a TFT-LCD Unit Cell for LCD TV Application

In this article, we present a novel scheme for automatic generation of an equivalent circuit for unit cell of LCD-TV. In order to automatically extract a circuit model, a computer program generates an electrical connectivity of resistors and capacitors from the layout information through a so-called pattern analysis with electrode and port information. Thereafter, the Ericksen-Leslies equation and two types of Laplaces equation in the dielectric and conductor domain are solved by finite element method (FEM). Finally, we can obtain a resistive equivalent circuit and a capacitive equivalent circuit in an independent manner. For combining two types of independent equivalent circuits, we propose a node insertion algorithm which enables us to generate an equivalent RC circuit without increasing the capacitive elements.

A Compact Model for Circuit Simulation of TFT-LCD Panel

In this paper, we report a novel compact SPICE model for circuit simulation of LCD-TVs. In this work, we generated a SPICE model for a unit cell of TFT-LCD by taking all of parasitic capacitances and resistances into account. In order to extract circuit model from a unit cell, an electrical connectivity of resistors and capacitors was generated through the pattern analysis data including electrode and port data, followed by the calculation of the parasitics using a finite element method (FEM). Moreover, we employed a piecewise linear voltage-controlled capacitor model with calculated values in order to take voltage dependency of LC capacitance into account. Consequently, we generated a new kickback model which considers the influence of adjacent bus lines.

Topography simulation for structural analysis using cell advancing method

In this paper, we propose a novel method for topography simulation in micro-electronic processes such as deposition and etching processes. The proposed scheme comprises of calculating the forward and backward movement of the surface and converting the cell structure into a tetrahedral mesh structure with topological information. Memory requirements are mitigated through a dynamic allocating scheme, which takes only the surface cells under consideration. For the removal of cells, a fixed time step is employed while volume remains in the surface cells. A spillover algorithm has also been devised in order to consider the case when more volume has to be removed from a cell during a single time step. Our proposed scheme was applied to the cases such as the construction of a TFT-LCD structure, ROM and a DRAM cell. A numerical simulator was interfaced with the topography simulator in order to investigate the successful meshing operation form the cell structure. For exemplary application, parasitic capacitances were extracted from a test wafer structure having 4 metal lines embedded in two types of non-planar dielectric layer. The simulation result exhibited about maximum 8% error, which seems to be relatively small in comparison to the planar dielectric layer.

Numerical Simulation on a Novel Cell Structure: Chevron HAN-FFS Mode LCD Cell Structure by TechWiz LCD

In this paper, a novel cell structure, named as chevron hybrid alignment nematic by fringing field switching (HAN-FFS), is proposed for realizing higher transmittance and wide-viewing angle. The proposed structure comprises a modified pixel electrode with grooves at an angle of 45° in upper part and − 45° in lower part of the one cell. Moreover, it has vertical surface in the middle of the cell. Transmittance of the chevron HAN-FFS had about 1.2 times than that of wedge-shaped HAN-FFS. And the saturation time is shorter for the chevron HAN-FFS than for the wedge-shaped HAN-FFS.

An extracting capacitance in a stacked DRAM cell by numerical method

This paper reports a methodology and its application for extracting the capacitance of a stacked DRAM cell structure by a numerical technique. To calculate the cell and parasitic capacitance in a stacked DRAM cell, we employed the finite element method (FEM), and to generate a complicated three-dimensional mesh structure, we used a graphic user interface, a topography simulator and three dimensional grid generator. A concave cylindrical DRAM cell capacitor with a minimum feature size of 0.25 /spl mu/m was chosen as a test vehicle to check the validity of the simulation. In this work, 62 parasitic capacitance values with 4 cell capacitance values were extracted from a stacked DRAM cell structure.