Sultan R. Helmi

A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology

A fully integrated broadband power amplifier (PA) is implemented in a standard 45-nm CMOS SOI technology. The PA is designed using a dynamically biased stacked SOI transistor approach, which constructively adds drain-source voltage signals of individual transistors while keeping their gate voltages within source and drain voltage limits. The design overcomes both low gate-oxide breakdown and low source-drain reach through voltages of nanoscale CMOS transistors. The number, size, and topology of transistors in the stack are optimized to deliver a relatively high linear output power over a wide range of frequencies. The amplifier under a supply voltage of 4.5 V measures a flat gain of 6 dB with -1-dB bandwidth of 6 to 26.5 GHz ( X-band to K-band). At 18 GHz, the PA under a supply voltage of 7.2 V measures a saturated output power (PSAT) of 26.1 dBm ( ~ 400 mW), a linear output power (P1 dB) of 22.5 dBm, and a peak power-added efficiency (PAE) of 11%. With a lower power supply voltage of 4.5 V, the PAE increases to more than 20% and stays above 17% with relatively constant PSAT and P1 dB for several measured frequencies in the range of 6 to 20 GHz. The PA occupies an active chip area of only 0.16 mm2.

A Wideband RF Power Amplifier in 45-nm CMOS SOI Technology With Substrate Transferred to AlN

A wideband radio frequency power amplifier (RF PA) is implemented with a stack of 16 low-breakdown-voltage thin-oxide transistors in a standard 45-nm CMOS SOI technology. A combination of dynamic-biasing and stacking prevents all breakdown mechanisms when the PA operates under large voltage swings and facilitates an output impedance close to 50 Ω without a need for an output-matching network. Using a post-fabrication process, the conductive Si substrate of the CMOS SOI PA is etched away and replaced by a semi-insulating aluminum nitride (AlN) substrate to reduce the effect of substrate parasitic capacitances and improve the PAs performance. A small-signal gain of 12.2 dB at 1.8 GHz is achieved with a - 3-dB bandwidth from 1.5 to 2.6 GHz. For high-reliability operation, the PA is biased with a 15-V power supply and a small transistor current density of 0.2 mA/μm and delivers a saturated output power (PSAT) of 30.2 dBm and a peak power-added efficiency (PAE) of 23.8%. For a wide range of measured frequencies from 1.5 to 2.4 GHz and under a lower supply voltage of 12 V, PSAT and P1 dB remain above 27.9 and 24.8 dBm, respectively, with peak PAE above 20%. In terms of output power, efficiency, and linearity, the CMOS PA on AlN substrate outperforms its Si counterpart, while both PAs deliver good power performance despite utilizing thin-oxide low-breakdown-voltage transistors.

A Wideband Power Amplifier in 45 nm CMOS SOI Technology for X Band Applications

A fully-integrated wideband power amplifier (PA) operating in 9-15 GHz range is implemented in a standard 45 nm CMOS SOI technology. The PA is designed with three dynamically-biased stacked Cascode cells (6 stacked transistors) to overcome the low breakdown voltages of nanoscale CMOS transistors. The stacked Cascode cells ensure stable operation and facilitate high gain, and high optimum load impedance, leading to high output power, high efficiency and good linearity characteristics over the entire bandwidth. The unbalanced amplitude and phase of drain-source voltage signals caused by internodal parasitic capacitance are equalized by adjusting the sizing of transistors. With a supply voltage of 4.8 V at 12 GHz, the measured saturated output power and linear power are 22.5 dBm and 19.2 dBm, respectively, while the peak power-added efficiency (PAE) is 19.2%. At a reduced power supply of 3.6 V, the PA achieves peak PAE of 25.7% where the drain efficiency reaches 40.7%. Including its pads, the PA occupies a compact chip area of 0.22 mm2.

High-Efficiency Microwave and mm-Wave Stacked Cell CMOS SOI Power Amplifiers

Design and implementation of high-efficiency microwave and mm-wave CMOS silicon-on-insulator (SOI) power amplifiers (PAs) based on a stacked cell approach is presented. Two stacked cell PAs have been implemented in GlobalFoundries 45-nm CMOS SOI technology. The first PA operating at K-band (24-28 GHz) is designed with three stacked triple Cascode cells. Each cell uses three standard transistors with separate layout. At 24 GHz, the K-band PA biased under a supply voltage of 10.8 V measures a maximum linear power gain of 13 dB, a saturated output power PSAT of 25.3 dBm, a -1-dB output power P1dB of 23.8 dBm, and a peak power-added efficiency (PAE) of 20%. The second PA targeted at U-band frequencies is designed with two stacked triple Cascode cells. Transistors in each cell have a combined layout that reduces parasitic capacitances, leading to significant improvement in the PAE at mm-wave frequencies. The U-band PA operates from 42 to 54 GHz. At 46 GHz, and under a supply voltage of 6 V, it measures a saturated output power (PSAT) of 22.4 dBm, a linear gain of 17.4 dB, and an unprecedented peak PAE of 42%.

A stacked Cascode CMOS SOI power amplifier for mm-wave applications

A millimeter-wave power amplifier (PA) implemented in a commercial 45nm CMOS SOI technology is presented. The PA design is based on stacking of two dynamically-biased Cascode transistor cells where drain-source voltages of individual transistors are added constructively to increase the output power. The PA output impedance is the sum of the output impedances of the two Cascode cells and is optimized to match to a 50 Ω load. At the operating frequency of 50 GHz and under a power supply of 4 V, the PA provides a saturated output power PSAT of 19 dBm (~80 mW), a -1dB output compression point (P1dB) of 16.3 dBm and a peak power-added efficiency (PAE) and drain efficiency (DE) of 28% and 40%, respectively.

Stacking the Deck for Efficiency: RF- to Millimeter-Wave Stacked CMOS SOI Power Amplifiers

The emerging demand for high-capacity wireless mobile communication and the advent of the Internet of Things and fifthgeneration communication standards have motivated the development of high-performance transceivers. The power amplifier (PA) is the most critical part in the transmit path and dominates the transceivers performance, including coverage range, data rate, spectrum compliance, and dc power dissipation. Integration capability and the relatively low cost of complementary-metal-oxide-semiconductor (CMOS) technology, on the other hand, have propelled it into the wireless market. CMOS technology enables complete system-on-chip solutions, resulting in a simple front-end assembly process, straightforward testing, and improved reliability. Today, in addition to the baseband, including the modulator/demodulator circuit, a big portion of the RF front end of the transceiver circuit is implemented in CMOS technology.

A fully-integrated 18 GHz class-E power amplifier in a 45 nm CMOS SOI technology

A fully-integrated Class-E power amplifier (PA) operating at 18 GHz is implemented in a standard 45 nm CMOS SOI technology. The PA is designed using differential Cascode topology with cross-coupled capacitors for Gate-Drain capacitance neutralization. The measured single-ended saturated power (PSAT) under a supply voltage of 2 V is 15.9 dBm (differential PSAT of 18.9 dB) and the 1-dB single-ended compression power (P1dB) is 13.3 dBm, with a peak power added efficiency (PAE) of 41.4%. The GateDrain capacitance neutralization technique facilitates the class-E operation and improves the PAE by ~20%.

A fully-integrated high power wideband power amplifier in 0.25 μm CMOS SOS technology

A fully-integrated wideband power amplifier (PA) is implemented in 0.25 μm CMOS silicon-on-sapphire (SOS) technology. The PA is designed with 4 stacked dynamically biased Cascode cells to increase the overall output voltage swing as well as the output impedance. The fully-insulating substrate in the SOS process significantly suppresses the effect of parasitic capacitance and hence minimizes the amplitude and phase differences among drain-source voltage waveforms across each transistor. The PA measures a saturated output power (PSAT) of 34.4 dBm (2.75 W) at 1.4 GHz with a peak PAE and corresponding DE of 38% and 48%, respectively, when biased under a 16 V supply. The measured output power is above 33 dBm (2 W) from 1 to 1.8 GHz. The linearity of the PA is measured with both uplink WCDMA and 10 MHz QPSK LTE signals at 1.4 GHz. The measured output power at ACLR of -33 dBc is 29.2 dBm for the WCDMA signal and 26.3 dBm for the LTE signal. The stacked PA occupies a compact chip area of 2.2 mm2.

A highly efficient mm-wave CMOS SOI power amplifier

Three mm-wave power amplifiers (PAs), each with 6 stacked transistors, are implemented in Global Foundries 45 nm CMOS SOI technology. As experimentally demonstrated, the design with two triple-Cascode cells with combined transistor layouts achieves the best power performance among the three designs. It achieves a power-added efficiency (PAE) of higher than 40% at 46 GHz and a relatively good power performance from 42 to 54 GHz. At 46 GHz the PA, biased under 6 V, measures a saturated output power (PSAT) of 22.4 dBm, a linear gain of 17.4 dB, a peak PAE of 42%, and a drain efficiency (DE) of 49%. Under a smaller supply voltage of 4.8 V, PSAT is reduced to 20 dBm while DE and peak PAE increase to 53% and 45%, respectively.

A 1.8GHz stacked power amplifier in 45nm CMOS SOI technology with substrate-transferred to AlN

A 1.8GHz power amplifier (PA) is implemented with a stack of 16 dynamically-biased thin-oxide transistors (tox = 1.16nm) in a standard 45nm CMOS SOI process. The stack configuration increases the overall breakdown voltage as well as the output impedance. The conductive Si substrate of the PA fabricated in a standard 45nm CMOS SOI process is etched and replaced by Aluminum Nitride (AlN) substrate to reduce the adverse effect of parasitic capacitances. The PA delivers a saturated output power (PSAT) of 26.5 dBm and a peak power added efficiency (PAE) of 19% at 1.8GHz when biased with high supply voltage (VDD = 12V) and low drain current for satisfying high-reliability requirements. The performance is comparable with reported PAs despite using very low-breakdown voltage transistors.