Sumantra Seth

An integrated linear RF power detector

An integrated RF power detector used in wireless communication is presented. The detector uses a unique replica circuitry to compensate for any changes in process or temperature. This results in a high degree of accuracy and a higher dynamic range. The detector has more than 25 dB of dynamic range within +/- 0.5 dB accuracy and is placed in the die along with the power amplifier in a BiCMOS process. The detector runs up to 7 GHz in simulation, though it is tested at 2.4 GHz here. It runs of a 3 V supply and consumes less than 5 mA.

A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process

A 2GHz wide input dynamic range (25%-75%) duty cycle corrector (DCC) circuit with ±2% output duty cycle accuracy is presented. This DCC circuit supports input frequency ranging from 1GHz to 2GHz. The proposed circuit is implemented in 45nm low voltage (0.9V to 1.4V) digital CMOS process. Presented DCC consumes only 1.4mW and occupies 0.01 mm2 area. Built-in-self test method is used to test this circuit in production and shows 99.98% pass percentage in silicon.

A differential self-biased slew rate controlled driver for accurate cross-over and rise-fall time matching

A self biased cross coupled 12Mbps 3.3V differential voltage driver presented with <;+/-3% rise-fall time mismatch for paired transitions ensuring accurate cross over voltage. Implemented in 45nm CMOS technology without 3.3V gate oxide device, design occupies 0.083 mm2 and consumes <; 15mW for 50pF load with 6MHz clock pattern. This architecture achieves a ~1.57X rise-fall time variation over 12X load capacitor variation across process, voltage and temperature.

A low power high speed envelope detector for serial data systems in 45nm CMOS

A low power, high speed (480Mbps) envelope detector for serial data systems such as USB2.0 is presented in this paper. The proposed architecture is based on a high frequency rectifier implementation along with a comparator and offers about 50% power and area saving compared to prior implementations using multiple comparators. A calibration scheme to make the envelope detector process, voltage and temperature independent is discussed. This architecture can be used for any high frequency serial interface requiring envelope detection. The circuit is implemented in 45nm CMOS technology and consumes 2.5mW power and occupies 0.015 mm2 area.